Deposition process for piezoelectric coatings

Patent metadata

Field	Value
Publication number	US-12389797-B2
Application number	US-201917288110-A
Country	US
Kind code	B2
Filing date	Sep 18, 2019
Priority date	Oct 26, 2018
Publication date	Aug 12, 2025
Grant date	Aug 12, 2025

Abstract

A method to deposit a coating including a material with highly oriented microstructure, the method including at least the following sequence of process steps: providing a flat substrate into a first vacuum processing chamber; etching one surface of the substrate by physical vapor etching; depositing a first metallic layer on the etched substrate surface by sputtering in a first metal deposition step; annealing the first metallic layer at an annealing temperature at least 50° C. higher than a compound deposition temperature of the subsequent compound deposition step; depositing a first compound layer at the compound deposition temperature on the outer surface of the first metallic layer by reactive sputtering in a first compound deposition step; and depositing a second metallic layer on the outer surface of the first compound layer by sputtering in a second metal deposition step.

First claim

What is claimed is:

1. A method to deposit a coating comprising a highly oriented crystalline material comprising at least the following sequence of process steps:
providing a flat substrate into a first vacuum processing chamber;
etching one surface of the substrate by physical vapor etching (PVE);
depositing a first metallic layer on the etched substrate surface by sputtering in a first metal deposition step;
annealing the first metallic layer in an annealing step;
depositing a first compound layer, after the annealing step, at a compound deposition temperature on the outer surface of the first metallic layer by reactive sputtering in a first compound deposition step; and
depositing a second metallic layer on the outer surface of the first compound layer by sputtering in a second metal deposition step,
wherein the first metallic layer is annealed at an annealing temperature at least 50° C. higher than a compound deposition temperature.

2. The method according to claim 1 , wherein a seed layer (Seed) is provided by metallic or reactive sputtering between the PVE-step and the first metal deposition step.

3. The method according to claim 1 , wherein at least one of the metallic layers is deposited to comprise as main elements at least one of molybdenum (Mo), ruthenium (Ru), platinum (Pt), aluminum (Al), tungsten (W) or a mixture thereof.

4. The method according to claim 1 , wherein the first metallic layer is deposited as a molybdenum (Mo) layer.

5. The method according to claim 1 , wherein the compound layer comprises as main elements aluminum (Al), or aluminum (Al) and at least one of chromium (Cr), scandium (Sc), magnesium (Mg), hafnium (Hf), as a metal or alloy and nitrogen (N) as a nonmetal.

6. The method according to claim 1 , wherein the compound layer is one of AlN, AlScN, AlCrN, or AlMgHfN.

7. The method according to claim 2 , wherein the seed layer is deposited as one of AlN, AlScN, AlCrN or Titanium (Ti).

8. The method according to claim 1 , wherein for the process temperature T COMP of the compound deposition step the following is valid:
200° C.≤T COMP ≤500° C.

9. The method according to claim 1 , wherein for the annealing temperature T A of the annealing step the following is valid:
T A ≤1000° C.

10. The method according to claim 1 , wherein further subsequent process steps are applied in different process chambers of a vacuum system.

11. The method according to claim 1 , wherein the annealing step is applied in a separate annealing oven.

12. The method according to claim 1 , wherein a further processing step is applied in a separate processing system.

13. The method according to claim 12 , wherein the further processing step comprises a structuring step of the first metallic layer before the first compound layer is deposited.

14. The method according to claim 1 , wherein after the annealing step one or more further PVE-steps are applied to a metallic surface.

15. The method according to claim 1 , wherein the PVE-step comprises an inductively coupled plasma etching (ICPE).

16. The method according to claim 1 , wherein the bulk stress of a piezoelectric coating is set in a range from −500 to +500 MPa.

17. A method to produce a coated substrate comprising the deposition method according to claim 1 , the coating having piezoelectric properties.

18. The method according to claim 17 , wherein the substrate is a wafer.

19. The method according to claim 17 , wherein the coated substrate is part of a piezoelectrical device used for microphones, electrical frequency filters, sensors or actuators.

20. The method according to claim 14 , wherein the one or more further PVE-steps comprises an inductively coupled plasma etching (ICPE).

Assignees

• Evatec Ag

Inventors

• Trajcevski Boris

Classifications

• H10N30/708

  Intermediate layers, e.g. barrier, adhesion or growth control buffer layers · CPC title

• H10N30/853

  Ceramic compositions · CPC title

• H10N30/076 Primary

  by vapour phase deposition · CPC title

• C23C14/5806

  Thermal treatment · CPC title

• C23C14/025

  Metallic sublayers · CPC title