Dummy pixel circuit, display panel and display device

Patent metadata

Field	Value
Publication number	US-12389684-B2
Application number	US-202117915421-A
Country	US
Kind code	B2
Filing date	Oct 29, 2021
Priority date	Apr 7, 2021
Publication date	Aug 12, 2025
Grant date	Aug 12, 2025

Abstract

Provided is a dummy pixel circuit. The dummy pixel circuit is applicable to a display panel provided with two through vias and disposed between the two through vias, and includes a pixel sub-circuit and a dummy sub-circuit. The pixel sub-circuit includes one or more first transistors, wherein a control electrode of the first transistor is electrically connected to the first gate line. The dummy sub-circuit includes one or more second transistors, wherein a control electrode of the dummy sub-circuit is electrically connected to the first gate line, a first electrode of the second transistor is electrically connected to a first electrode of a corresponding one of the one or more first transistors, and a second electrode of the second transistor is electrically connected to a second electrode of the corresponding first transistor. One of the first transistors corresponds to at least one of the second transistors.

First claim

What is claimed is:

1. A dummy pixel circuit, applicable to a display panel provided with two through vias, the dummy pixel circuit being disposed between the two through vias and comprising:
a pixel sub-circuit comprising one or more first transistors, wherein a control electrode of the first transistor is electrically connected to a first gate line, the first gate line being provided with a bend that bypasses the through via; and
a dummy sub-circuit comprising one or more second transistors, wherein a control electrode of the second transistor is electrically connected to the first gate line, a first electrode of the second transistor is electrically connected to a first electrode of a corresponding one of the one or more first transistors, and a second electrode of the second transistor is electrically connected to a second electrode of the corresponding first transistor;
wherein each of the one or more first transistors corresponds to at least one of the one or more second transistors.

2. The dummy pixel circuit according to claim 1 , wherein
the first transistor comprises a first switch transistor and a first compensation transistor, and the second transistor comprises a second switch transistor and a second compensation transistor; and
the second switch transistor corresponds to the first switch transistor, and the second compensation transistor corresponds to the first compensation transistor.

3. The dummy pixel circuit according to claim 2 , wherein orthographic projections of the first switch transistor and the first compensation transistor on a first surface are between an orthographic projection of the first switch transistor on the first surface and an orthographic projection of the first compensation transistor on the first surface, the first surface being a surface of a base substrate where the dummy pixel circuit is disposed.

4. The dummy pixel circuit according to claim 3 , wherein
orthographic projections of an active layer of the second compensation transistor and an active layer of the first compensation transistor on the first surface form a rectangular ring; and
the orthographic projection of the active layer of the second compensation transistor on the first surface form two connected sides of the rectangular ring, and the orthographic projection of the active layer of the first compensation transistor form the other two sides of the rectangular ring.

5. The dummy pixel circuit according to claim 4 , wherein
an extension direction of one of the other two sides of the rectangular ring is consistent with an extension direction of a connection line in a source-drain layer; and
one of the other two sides of the rectangular ring is at least partially overlapped with an orthographic projection, of the connection line in the source-drain layer, on the first surface.

6. The dummy pixel circuit according to claim 3 , wherein control electrodes of the second compensation transistor and the first compensation transistor are respectively disposed on two sides of the first gate line to which the first switch transistor is connected.

7. The dummy pixel circuit according to claim 6 , wherein a connection line between a center of the control electrode of the second compensation transistor and a center of the control electrode of the first compensation transistor is perpendicular to the first gate line.

8. The dummy pixel circuit according to claim 1 , wherein
the first transistor comprises a first reset transistor and a second reset transistor, and the second transistor comprises a third reset transistor and a fourth reset transistor;
wherein the third reset transistor corresponds to the first reset transistor, and the fourth reset transistor corresponds to the second reset transistor.

9. The dummy pixel circuit according to claim 1 , wherein a number of the second transistors ranges from 1 to 4.

10. The dummy pixel circuit according to claim 1 , wherein
the first electrode of the first transistor and a first electrode of the second transistor connected thereto are disposed in a same layer; and
the second electrode of the first transistor and a second electrode of the second transistor connected thereto are disposed in a same layer.

11. The dummy pixel circuit according to claim 10 , wherein
the first electrode of the first transistor and a first electrode of a corresponding one of the one or more second transistors are connected together by a trace, and the second electrode of the first transistor and a second electrode of the corresponding second transistor are connected together by a trace.

12. The dummy pixel circuit according to claim 10 , wherein
the first transistor and the second transistor share a same first electrode, and the first transistor and the second transistor share a same second electrode.

13. A display panel, comprising: a dummy pixel circuit and a first gate line, wherein the display panel is provided with two through vias therein, the first gate line is provided with a bend that bypasses the through via, the dummy pixel circuit is disposed between the two through vias; and the dummy pixel circuit comprises:
a pixel sub-circuit comprising one or more first transistors, wherein a control electrode of the first transistor is electrically connected to the first gate line; and
a dummy sub-circuit comprising one or more second transistors, wherein a control electrode of the second transistor is electrically connected to the first gate line, a first electrode of the second transistor is electrically connected to a first electrode of a corresponding one of the one or more first transistors, and a second electrode of the second transistor is electrically connected to a second electrode of the corresponding first transistor;
wherein each of the one or more first transistors corresponds to at least one of the one or more second transistors.

14. The display panel according to claim 13 , further comprising: a pixel circuit and a second gate line; wherein
a length of the first gate line is greater than a length of the second gate line; and
the pixel circuit and the pixel sub-circuit have an identical circuit structure and the pixel circuit is electrically connected to the second gate line.

15. The display panel according to claim 13 , wherein
the first transistor comprises a first switch transistor and a first compensation transistor, and the second transistor comprises a second switch transistor and a second compensation transistor; and
the second switch transistor corresponds to the first switch transistor, and the second compensation transistor corresponds to the first compensation transistor.

16. The display panel according to claim 15 , wherein orthographic projections of the first switch transistor and the first compensation transistor on a first surface are between an orthographic projection of the first switch transistor on the first surface and an orthographic projection of the first compensation transistor on the first surface, the first surface being a surface of a base substrate where the dummy pixel circuit is disposed.

17. The display panel according to claim 16 , wherein
orthographic projections of an active layer of the second compensation transistor and an active layer of the first compensation transistor on the first surface form a rectangular ring; and
the orthographic projection of the active layer of the second compensation transistor on the first surface form two connected sides of the rectangular ring, and the orthographic projection of the active layer of the first compensation transistor form the other two side

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Yang Huijuan
• Liao Maoying
• Zhou Yang
• Bai Lu
• Dai Jie
• Cao Dan

Classifications

• H10D86/411 Primary

  characterised by materials, geometry or structure of the substrates · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title

• G09G2320/0233

  Improving the luminance or brightness uniformity across the screen · CPC title

• G09G3/32 Primary

  semiconductive, e.g. using light-emitting diodes [LED] · CPC title