Integrated circuit structure

Patent metadata

Field	Value
Publication number	US-12389666-B2
Application number	US-202418594735-A
Country	US
Kind code	B2
Filing date	Mar 4, 2024
Priority date	Apr 24, 2017
Publication date	Aug 12, 2025
Grant date	Aug 12, 2025

Abstract

A device includes a first transistor, a second transistor, and a dielectric structure. The first transistor is over a substrate and has a first gate structure. The second transistor is over the substrate and has a second gate structure. The dielectric structure is between the first gate structure and the second gate structure. The dielectric structure has a width increasing from a bottom position of the dielectric structure to a first position higher than the bottom position of the dielectric structure. A width of the first gate structure is less than the width of the dielectric structure at the first position.

First claim

What is claimed is:

1. A device, comprising:
a semiconductor fin extending from a semiconductor substrate;
a first transistor comprising a first gate structure over the semiconductor fin and a first source/drain region adjacent to the first gate structure;
a second transistor comprising a second gate structure over the semiconductor fin and a second source/drain region adjacent to the second gate structure; and
an isolation structure between the first source/drain region and the second source/drain region,
wherein the isolation structure extends above a top surface of the first source/drain region and a top surface of the second source/drain region,
wherein a width of the isolation structure increases from a bottom of the isolation structure to a first position,
wherein a width of the first gate structure is less than the width of the isolation structure at the first position, and
wherein the first position is disposed within the semiconductor fin.

2. The device of claim 1 , wherein the width of the isolation structure decreases from the first position to a second position that is above the first position.

3. The device of claim 2 , wherein the width of the isolation structure increases from the second position to a third position that is above the second position.

4. The device of claim 1 , wherein the isolation structure extends along sidewalls of the first gate structure and the second gate structure.

5. The device of claim 1 , wherein the bottom of the isolation structure is below bottom surfaces of the first source/drain region and the second source/drain region.

6. The device of claim 1 , wherein the bottom of the isolation structure is disposed in the semiconductor fin.

7. The device of claim 1 , wherein the bottom of the isolation structure is disposed in a semiconductor substrate under the semiconductor fin.

8. A device, comprising:
a semiconductor fin extending from a semiconductor substrate; and
an isolation structure laterally disposed between two adjacent gate structures over the semiconductor fin,
wherein a width of the isolation structure increases from a bottom of the isolation structure to a first position, the bottom of the isolation structure and the first position each being disposed within the semiconductor fin, and wherein a width of a first gate structure of the two adjacent gate structures is less than the width of the isolation structure at the first position, wherein the isolation structure comprises a dielectric material that extends continuously from a first sidewall of the isolation structure at the first position to a second sidewall of the isolation structure at the first position.

9. The device of claim 8 , wherein the width of the isolation structure decreases from the first position to a second position, the second position being above the first position.

10. The device of claim 8 , wherein a first sidewall of the first gate structure is laterally separated from the isolation structure, and wherein a second sidewall of a second gate structure of the two adjacent gate structures is laterally separated from the isolation structure.

11. The device of claim 8 , wherein the isolation structure is not overlapped by any gate structures.

12. The device of claim 8 , wherein no gate structures are disposed between the two adjacent gate structures.

13. The device of claim 8 , wherein the isolation structure extends at least to a top surface of the first gate structure.

14. The device of claim 8 , wherein the two adjacent gate structures comprise a second gate structure immediately adjacent to the first gate structure.

15. A device, comprising:
a first transistor in a first region of a semiconductor fin;
a second transistor in a second region of the semiconductor fin; and
a dielectric structure isolating the first transistor from the second transistor, wherein the dielectric structure comprises a non-linear sidewall profile in the semiconductor fin in a cross-sectional view, the non-linear sidewall profile comprising a first segment, a second segment over the first segment, and a third segment over the first segment,
wherein the first segment and the second segment define an obtuse angle that faces a center of the dielectric structure, and
wherein the second segment and the third segment define an angle that is different from the obtuse angle defined by the first segment and the second segment.

16. The device of claim 15 , wherein the first segment and the second segment meet at a first position, and wherein the first position is disposed in the semiconductor fin.

17. The device of claim 16 , wherein a width of the dielectric structure at the first position is larger than a width of the dielectric structure at a second position, and wherein the second position is below the first position.

18. The device of claim 15 , wherein the third segment is at least partially disposed in the semiconductor fin.

19. The device of claim 15 , wherein the first transistor comprises a first gate structure, and wherein the dielectric structure extends at least to a level of a top surface of the first gate structure.

20. The device of claim 15 , wherein the angle defined by the second segment and the third segment is an obtuse angle that faces away from the center of the dielectric structure.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Kuei-Ming
• Hsieh Rei-Jay
• Wu Cheng-Han
• Lin Chie-Luan

Classifications

• H10W10/0145 Primary

  of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence) · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D84/853

  comprising FinFETs · CPC title

• H10D84/0193

  the components including FinFETs · CPC title

• H10D84/0151

  Manufacturing their isolation regions · CPC title