Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-12389631-B2
Application number	US-202318522543-A
Country	US
Kind code	B2
Filing date	Nov 29, 2023
Priority date	Oct 16, 2009
Publication date	Aug 12, 2025
Grant date	Aug 12, 2025

Abstract

An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured using a thin film transistor in which a channel formation region is formed using an oxide semiconductor which becomes an intrinsic or substantially intrinsic semiconductor by removing impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than that of a silicon semiconductor. With use of a thin film transistor using a highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device with low power consumption due to leakage current can be realized.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a first transistor over a substrate having an insulating surface, the first transistor comprising a first oxide semiconductor layer where a channel formation region is provided and a first gate electrode layer;
a second transistor over the substrate, the second transistor comprising a second oxide semiconductor layer where a channel formation region is provided and a second gate electrode layer; and
a first conductive layer electrically connected to the first oxide semiconductor layer,
wherein the first gate electrode layer is over the first oxide semiconductor layer,
wherein the second gate electrode layer is over the second oxide semiconductor layer,
wherein a first insulating layer is provided between the first oxide semiconductor layer and the insulating surface, where the first insulating layer overlaps the channel formation region in the first oxide semiconductor layer,
wherein a second conductive layer is provided between the first insulating layer and the insulating surface, where the second conductive layer overlaps the channel formation region in the first oxide semiconductor layer,
wherein the first insulating layer is between the second oxide semiconductor layer and the insulating surface, where the first insulating layer overlaps the channel formation region in the second oxide semiconductor layer,
wherein no conductive layer which overlaps the channel formation region in the second oxide semiconductor layer is provided between the first insulating layer and the insulating surface,
wherein a channel length of the first transistor is longer than a channel length of the second transistor,
wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises indium, gallium, and zinc, and
wherein the first gate electrode layer, the second gate electrode layer, and the first conductive layer are provided on a same layer and comprise a same material.

2. The semiconductor device according to claim 1 ,
wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer are over and in direct contact with the first insulating layer.

3. The semiconductor device according to claim 1 ,
wherein a size of crystal grains in each of the first oxide semiconductor layer and the second oxide semiconductor layer is greater than or equal to 1 nm and smaller than or equal to 20 nm.

4. The semiconductor device according to claim 1 ,
wherein a hydrogen concentration in each of the first oxide semiconductor layer and the second oxide semiconductor layer is lower than or equal to 5×10 19 /cm 3 .

5. A semiconductor device comprising:
a first insulating layer over a substrate;
a first transistor over the first insulating layer, the first transistor comprising a first oxide semiconductor layer where a channel formation region is provided and a first gate electrode layer;
a second transistor over the first insulating layer, the second transistor comprising a second oxide semiconductor layer where a channel formation region is provided and a second gate electrode layer; and
a first conductive layer electrically connected to the first oxide semiconductor layer,
wherein the first gate electrode layer is over the first oxide semiconductor layer,
wherein the second gate electrode layer is over the second oxide semiconductor layer,
wherein a second insulating layer is provided between the first oxide semiconductor layer and the first insulating layer, where the second insulating layer overlaps the channel formation region in the first oxide semiconductor layer,
wherein a second conductive layer is provided between the second insulating layer and the first insulating layer, where the second conductive layer overlaps the channel formation region in the first oxide semiconductor layer,

wherein the second insulating layer is between the second oxide semiconductor layer and the first insulating layer, where the second insulating layer overlaps the channel formation region in the second oxide semiconductor layer,
wherein no conductive layer which overlaps the channel formation region in the second oxide semiconductor layer is provided between the second insulating layer and the first insulating layer,
wherein a channel length of the first transistor is longer than a channel length of the second transistor,
wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises indium, gallium, and zinc, and
wherein the first gate electrode layer, the second gate electrode layer, and the first conductive layer are provided on a same layer and comprise a same material.

6. The semiconductor device according to claim 5 ,
wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer are over and in direct contact with the second insulating layer.

7. The semiconductor device according to claim 5 ,
wherein a size of crystal grains in each of the first oxide semiconductor layer and the second oxide semiconductor layer is greater than or equal to 1 nm and smaller than or equal to 20 nm.

8. The semiconductor device according to claim 5 ,
wherein a hydrogen concentration in each of the first oxide semiconductor layer and the second oxide semiconductor layer is lower than or equal to 5×10 19 /cm 3 .

9. A semiconductor device comprising:
a first transistor over a first insulating layer, the first transistor comprising a first oxide semiconductor layer where a channel formation region is provided and a first gate electrode layer;
a second transistor over the first insulating layer, the second transistor comprising a second oxide semiconductor layer where a channel formation region is provided and a second gate electrode layer; and
a first conductive layer electrically connected to the first oxide semiconductor layer,
wherein the first gate electrode layer is over the first oxide semiconductor layer,
wherein the second gate electrode layer is over the second oxide semiconductor layer,
wherein a second insulating layer is provided between the first oxide semiconductor layer and the first insulating layer, where the second insulating layer overlaps the channel formation region in the first oxide semiconductor layer,
wherein a second conductive layer is provided between the second insulating layer and the first insulating layer, where the second conductive layer overlaps the channel formation region in the first oxide semiconductor layer,

wherein the second insulating layer is between the second oxide semiconductor layer and the first insulating layer, where the second insulating layer overlaps the channel formation region in the second oxide semiconductor layer,
wherein no conductive layer which overlaps the channel formation region in the second oxide semiconductor layer is provided between the second insulating layer and the first insulating layer,
wherein a channel length of the first transistor is longer than a channel length of the second transistor,
wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises indium, gallium, and zinc, and
wherein the first gate electrode layer, the second gate electrode layer, and the first conductive layer are provided on a same layer and comprise a same material.

10. The semiconductor device according to claim 9 ,
wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer are over and in direct contact with the second insulating layer.

11. The semiconductor device according to claim 9 ,
wherein a size of crystal grains in each of the first oxide semiconductor layer and the secon

Assignees

• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Koyama Jun
• Miyake Hiroyuki
• Takahashi Kei
• Toyotaka Kouhei
• Tsubuku Masashi
• Noda Kosei
• Kuwabara Hideaki

Classifications

• H10W44/248

  for antennas · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H02M3/07

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G11C7/00

  Arrangements for writing information into, or reading information out from, a digital store (G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413) · CPC title