Semiconductor memory devices and methods for manufacturing the same

Patent metadata

Field	Value
Publication number	US-12389584-B2
Application number	US-202217577120-A
Country	US
Kind code	B2
Filing date	Jan 17, 2022
Priority date	Jun 24, 2021
Publication date	Aug 12, 2025
Grant date	Aug 12, 2025

Abstract

A semiconductor memory device and a method for manufacturing the same. The semiconductor memory device may include a substrate, a first lower wire pattern and a first upper wire pattern stacked on the substrate, and spaced apart from each other; a second lower wire pattern and a second upper wire pattern stacked on the substrate, spaced apart from each other, and spaced apart from the first lower and upper wire patterns; a first gate line surrounding the first lower wire pattern and the first upper wire pattern; a second gate line surrounding the second lower wire pattern and the second upper wire pattern and spaced apart from the first gate line; a first lower source/drain area; a first upper source/drain area; and a first overlapping contact that electrically connects the first lower source/drain area, the first upper source/drain area and the second gate line to each other.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a substrate;
a first lower wire pattern and a first upper wire pattern sequentially stacked on the substrate, and spaced apart from each other, each extending in a first direction;
a second lower wire pattern and a second upper wire pattern sequentially stacked on the substrate, and spaced apart from each other, each extending in the first direction, the second lower wire pattern and the second upper wire pattern spaced apart from the first lower wire pattern and the first upper wire pattern in a second direction that intersects the first direction;
a first gate line extending in the second direction, and surrounding the first lower wire pattern and the first upper wire pattern;
a second gate line extending in the second direction, and surrounding the second lower wire pattern and the second upper wire pattern, the second gate line spaced apart from the first gate line in the second direction;
a first lower source/drain area having a first conductivity type, on one side surface of the first gate line, and connected to the first lower wire pattern;
a first upper source/drain area having a second conductivity type different from the first conductivity type, on one side surface of the first gate line, and connected to the first upper wire pattern; and
a first overlapping contact that electrically connects the first lower source/drain area, the first upper source/drain area and the second gate line to each other, wherein the first overlapping contact at least partially vertically overlaps the first gate line,
wherein the first gate line includes a first gate electrode and a recess capping pattern, wherein the recess capping pattern covers a top surface of the first gate electrode that overlaps the first overlapping contact,
wherein the second gate line includes a second gate electrode and a gate capping pattern, wherein the gate capping pattern covers a top surface of the second gate electrode,
wherein a vertical level of a bottom surface of the recess capping pattern is lower than a vertical level of a bottom surface of the gate capping pattern,
wherein a vertical level of a bottom surface of the first overlapping contact is lower than or equal to the vertical level of the bottom surface of the gate capping pattern, and
wherein the vertical level of the bottom surface of the first overlapping contact is higher than the vertical level of the bottom surface of the recess capping pattern.

2. The semiconductor memory device of claim 1 , wherein a top surface of the recess capping pattern and a top surface of the gate capping pattern are coplanar with each other.

3. The semiconductor memory device of claim 1 , wherein the vertical level of the bottom surface of the recess capping pattern is higher than or equal to a vertical level of a top surface of the first upper wire pattern.

4. The semiconductor memory device of claim 1 , wherein the first overlapping contact includes:
a first extension portion that extends in the first direction and overlaps the first lower wire pattern and the first upper wire pattern; and
a second extension portion that extends from the first extension portion in the second direction and overlaps the first gate line and the second gate line.

5. The semiconductor memory device of claim 1 , wherein the first conductivity type is a n-type, and the second conductivity type is a p-type.

6. The semiconductor memory device of claim 1 , further comprising a separating insulating film that includes:
a first separating portion on one side of the first gate line that separates the first lower source/drain area and the first upper source/drain area from each other; and
a second separating portion on an opposite side of the first gate line,
wherein a vertical level of a top surface of the second separating portion is higher than a vertical level of a top surface of the first separating portion.

7. The semiconductor memory device of claim 6 , wherein the vertical level of the top surface of the second separating portion is higher than or equal to a vertical level of a top surface of the first upper wire pattern.

8. The semiconductor memory device of claim 1 , further comprising:
a third gate line extending in the second direction, and surrounding the first lower wire pattern and the first upper wire pattern, and spaced apart from the first gate line in the first direction;
a fourth gate line extending in the second direction, and surrounding the second lower wire pattern and the second upper wire pattern, and spaced apart from the third gate line in the second direction;
a second lower source/drain area having the first conductivity type, between the second gate line and the fourth gate line, and connected to the second lower wire pattern;
a second upper source/drain area having the second conductivity type, between the second gate line and the fourth gate line, and connected to the second upper wire pattern; and
a second overlapping contact that electrically connects the second lower source/drain area, the second upper source/drain area, and the third gate line to each other.

9. A semiconductor memory device comprising:
a substrate;
a first lower wire pattern and a first upper wire pattern sequentially stacked on the substrate, and spaced apart from each other, each extending in a first direction;
a second lower wire pattern and a second upper wire pattern sequentially stacked on the substrate, and spaced apart from each other, each extending in the first direction, the second lower wire pattern and the second upper wire pattern spaced apart from the first lower wire pattern and the first upper wire pattern in a second direction that intersects the first direction;
a first gate line extending in the second direction, and surrounding the first lower wire pattern and the first upper wire pattern;
a second gate line extending in the second direction, and surrounding the second lower wire pattern and the second upper wire pattern, wherein the second gate line is spaced apart from the first gate line in the second direction;
a first lower source/drain area having a first conductivity type, on one side of the first gate line, and connected to the first lower wire pattern;
a first upper source/drain area having a second conductivity type different from the first conductivity type, on one side of the first gate line, and connected to the first upper wire pattern;
a common contact extending in a third direction that intersects a top surface of the substrate, wherein the common contact is connected to the first lower source/drain area and the first upper source/drain area; and
an overlapping contact that electrically connects the common contact and the second gate line to each other, wherein the overlapping contact at least partially overlaps the first gate line,
wherein the first gate line includes a first gate electrode and a recess capping pattern, wherein the recess capping pattern covers a top surface of the first gate electrode that overlaps the overlapping contact,
wherein the second gate line includes a second gate electrode and a gate capping pattern, wherein the gate capping pattern covers a top surface of the second gate electrode,
wherein a vertical level of a bottom surface of the overlapping contact is lower than or equal to a vertical level of the bottom surface of the gate capping pattern, and
wherein the vertical level of the bottom surface of the overlapping contact is higher than a vertical level of the bottom surface of the recess capping pattern.

10. The semiconductor memory device of claim 9 , wherein the overlapping contact includes:
a first extension portion that extends in the first directio

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Sung Il
• Park Jae Hyun
• Kim Min Gyu
• Choi Do Young
• Ha Dae Won

Classifications

• H10D64/018

  Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates · CPC title

• H10D64/017 Primary

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D62/118

  Nanostructure semiconductor bodies · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title