Signal processing circuit

Patent metadata

Field	Value
Publication number	US-12389135-B2
Application number	US-202218580736-A
Country	US
Kind code	B2
Filing date	May 11, 2022
Priority date	Aug 19, 2021
Publication date	Aug 12, 2025
Grant date	Aug 12, 2025

Abstract

A signal processing circuit includes: a filter circuit that removes noise from a target signal; and a controller that controls the filter circuit. The filter circuit includes: a CMOS switch including a first MOSFET and a second MOSFET having different channel types and connected in parallel; and a capacitor electrically connected between an output of the CMOS switch and a ground potential. The controller switches a state of the CMOS switch between a first state in which the first MOSFET is in an ON state and a second state in which the first MOSFET is in an OFF state and the second MOSFET is in an ON state. An ON resistance value of the second MOSFET is higher than an ON resistance value of the first MOSFET.

First claim

The invention claimed is:

1. A signal processing circuit comprising:
a filter circuit configured to remove noise from a target signal; and
a controller configured to control the filter circuit,
wherein the filter circuit comprises:
a CMOS switch including a first MOSFET and a second MOSFET having different channel types and connected in parallel; and
a capacitor electrically connected between an output of the CMOS switch and a ground potential,
wherein the controller switches a state of the CMOS switch between a first state in which the first MOSFET is in an ON state and a second state in which the first MOSFET is in an OFF state and the second MOSFET is in an ON state, and
wherein an ON resistance value of the second MOSFET is higher than an ON resistance value of the first MOSFET.

2. The signal processing circuit according to claim 1 ,
wherein the controller switches the state of the CMOS switch from the first state to the second state while the capacitor is being charged by the target signal.

3. The signal processing circuit according to claim 1 , further comprising:
a light receiving element configured to generate and accumulate electric charge by being irradiated with light; and
an amplifier circuit configured to amplify an output signal of the filter circuit,
wherein the filter circuit receives, as the target signal, a signal corresponding to the electric charge accumulated by the light receiving element.

4. The signal processing circuit according to claim 1 , further comprising:
a light receiving element configured to generate and accumulate electric charge by being irradiated with light; and
an amplifier circuit configured to generate the target signal by amplifying a signal corresponding to the electric charge accumulated by the light receiving element, and supply the target signal to the filter circuit.

5. The signal processing circuit according to claim 4 ,
wherein the amplifier circuit comprises a setting circuit configured to set a reset level of the target signal.

6. The signal processing circuit according to claim 5 ,
wherein the setting circuit sets the reset level so that a voltage of the target signal varies within a range in which the ON resistance value of the second MOSFET is higher than the ON resistance value of the first MOSFET.

7. The signal processing circuit according to claim 1 , further comprising a setting circuit configured to set a reset level of the target signal.

8. The signal processing circuit according to claim 1 ,
wherein the first state is a state in which both the first MOSFET and the second MOSFET are in an ON state.

9. The signal processing circuit according to claim 1 ,
wherein the first MOSFET is a p-channel MOSFET, and the second MOSFET is an n-channel MOSFET.

10. The signal processing circuit according to claim 1 ,
wherein the first MOSFET is an n-channel MOSFET, and the second MOSFET is a p-channel MOSFET.

Assignees

• Hamamatsu Photonics Kk

Inventors

• Shimada Akihiro
• Mase Mitsuhito

Classifications

• H04N25/62

  Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels · CPC title

• H03K17/687

  the devices being field-effect transistors · CPC title

• H03H11/04

  Frequency selective two-port networks · CPC title

• H04N25/78 Primary

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title

• H04N25/618 Primary

  for random or high-frequency noise · CPC title