Negative bias circuit for power device driving

US12388434B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12388434-B2
Application numberUS-202318121528-A
CountryUS
Kind codeB2
Filing dateMar 14, 2023
Priority dateMar 14, 2023
Publication dateAug 12, 2025
Grant dateAug 12, 2025

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

Aspects of the disclosure relate to a negative bias circuit for power device driving. An apparatus may include a power source, a gate impedance path, a capacitor in series with the gate impedance path, and a clamping circuit for a transistor gate.

First claim

Opening claim text (preview).

What is claimed is: 1. A circuit for power device driving comprising: a totem pole driver; a gate impedance path, wherein the totem pole driver is connected with the gate impedance path, wherein the gate impedance path comprises a first path comprising an On resistor and a second path in parallel with the first path, wherein the second path comprises an Off resistor positioned upstream of and in series with a diode, wherein the Off resistor is directly connected to a cathode of the diode; a capacitor in series with the gate impedance path; a clamping circuit, wherein the clamping circuit clamps voltage of a transistor gate and the clamping circuit comprises a plurality of Zener diodes in a back-to-back series arrangement; and the transistor gate. 2. The circuit of claim 1 , wherein the clamping circuit is positioned between the totem pole driver and the gate impedance path. 3. The circuit of claim 1 , wherein the clamping circuit is positioned between the gate impedance path and the transistor gate. 4. The circuit of claim 1 , wherein the transistor gate comprises a silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) or n-channel MOSFET. 5. The circuit of claim 1 , wherein the transistor gate comprises a gallium nitride (GaN) transistor or insulated-gate bipolar transistor (IGBT). 6. The circuit of claim 1 , wherein the circuit is integrated into an electronic component of an electric vehicle, the electronic component comprising a direct current-direct current (DC-DC) converter. 7. The circuit of claim 1 , wherein the capacitor charges during an on-state of the circuit. 8. The circuit of claim 1 , wherein the circuit is integrated into an electronic component of an automobile. 9. The circuit of claim 1 , wherein the capacitor is positioned between a power source and the gate impedance path. 10. The circuit of claim 1 , wherein: the capacitor is positioned between a power source and the gate impedance path, and the clamping circuit is positioned between the gate impedance path and the transistor gate. 11. A circuit for power device driving comprising: a gate impedance path, wherein the gate impedance path comprises a first path comprising an On resistor and a second path in parallel with the first path, wherein the second path comprises an Off resistor positioned upstream of and in series with a diode, wherein the Off resistor is directly connected to a cathode of the diode; a capacitor in series with the gate impedance path; a clamping circuit, wherein the clamping circuit clamps voltage of a transistor gate and the clamping circuit comprises a plurality of Zener diodes in a back-to-back series arrangement; and the transistor gate. 12. The circuit of claim 11 , wherein the clamping circuit creates a charging current for the capacitor during an on-state of the circuit. 13. The circuit of claim 11 , wherein the clamping circuit is positioned between the gate impedance path and the transistor gate. 14. The circuit of claim 11 , wherein the transistor gate comprises a silicon carbide (SiC) metal-oxide semiconductor field-effect transistor (MOSFET). 15. The circuit of claim 11 , wherein the transistor gate comprises a gallium nitride (GaN) transistor. 16. The circuit of claim 11 , wherein the circuit is integrated into an electronic component of an electric vehicle, the electronic component comprising an on-board charger (OBC). 17. The circuit of claim 11 , wherein the circuit is integrated into an electronic component of an electric vehicle. 18. The circuit of claim 11 , wherein the circuit is integrated into an electronic component of an electric vehicle, the electronic component comprising an electronic inverter. 19. The circuit of claim 11 , wherein the capacitor is positioned between a power source and the gate impedance path. 20. The circuit of claim 11 , wherein: the capacitor is positioned between a power source and the gate impedance path, and the clamping circuit is positioned between the gate impedance path and the transistor gate.

Assignees

Inventors

Classifications

  • Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors (logic circuits H03K19/00; code converters H03M5/00, H03M7/00) · CPC title

  • without feedback from the output circuit to the control circuit · CPC title

  • the output circuit comprising more than one controlled field-effect transistor · CPC title

  • H03K17/063Primary

    in field-effect transistor switches · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US12388434B2 cover?
Aspects of the disclosure relate to a negative bias circuit for power device driving. An apparatus may include a power source, a gate impedance path, a capacitor in series with the gate impedance path, and a clamping circuit for a transistor gate.
Who is the assignee on this patent?
Rivian Ip Holdings Llc
What technology area does this patent fall under?
Primary CPC classification H03K17/6871. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 12 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 6 related publications on this page (citations in our corpus or others sharing the same primary CPC).