High voltage switch

Patent metadata

Field	Value
Publication number	US-12388433-B2
Application number	US-202318485149-A
Country	US
Kind code	B2
Filing date	Oct 11, 2023
Priority date	Nov 30, 2022
Publication date	Aug 12, 2025
Grant date	Aug 12, 2025

Abstract

The present disclosure relates to a high voltage bidirectional power switch circuit that includes a high voltage block coupled to a first terminal; and a resistance network including modules connected in parallel with each other between the high voltage block and a second terminal. Each module includes a precision resistor connected in series with a conduction channel of a resistance switching transistor; a first biasing resistor connected between a first conduction channel terminal and a control terminal of the resistance switching transistor; a second biasing resistor connected between a second conduction channel terminal and the control terminal; a body bias control circuit configured to control a bias of body diodes of the resistance switching transistor; a switchable sourcing current source; and a switchable sinking current source. Switches of the switchable sourcing current source and the switchable sinking current source receive switching signals to control the resistance switching transistor.

First claim

The invention claimed is:

1. A high voltage (HV) bidirectional power switch (BPS) circuit comprising:
a first terminal and a second terminal;
a HV block coupled to the first terminal, wherein the HV block comprises two HV transistors arranged in series in a BPS configuration; and
a resistance network comprising a plurality of switchable resistance modules connected in parallel with each other between the HV block and the second terminal, wherein each switchable resistance module comprises:
a precision resistor connected in series with a conduction channel of a resistance switching transistor;
a first biasing resistor connected between a first conduction channel terminal of the resistance switching transistor and a control terminal of the resistance switching transistor;
a second biasing resistor connected between a second conduction channel terminal of the resistance switching transistor and the control terminal of the resistance switching transistor;
a body bias control circuit configured to control the bias of body diodes of the resistance switching transistor;
a switchable sourcing current source comprising a first current source and a first source switch connected in series between a positive voltage supply terminal and the control terminal of the resistance switching transistor; and
a switchable sinking current source comprising a second current source and a second source switch connected in series between a negative voltage supply terminal and the control terminal of the resistance switching transistor,
wherein the first source switch and the second source switch are configured to receive switching signals to selectively enable or disable the resistance switching transistor.

2. The HV BPS circuit of claim 1 , wherein the switching signals comprise:
if the HV BPS circuit is set to an ON state, complementary switching signals for:
selectively enabling the first source switch and selectively disabling the second source switch; or
selectively disabling the first source switch and selectively enabling the second source switch; or

if the HV BPS circuit is set to an OFF state, disabling switching signals for disabling the first source switch and disabling the second source switch.

3. The HV BPS circuit of claim 1 , wherein, for each switchable resistance module, a resistance value of the first biasing resistor and a resistance value of the second biasing resistor are both greater than a resistance value of the precision resistor.

4. The HV BPS circuit of claim 1 , wherein the body bias control circuit comprises a body voltage selector circuit configured to:
select a voltage from:
a first voltage at the first conduction channel terminal; and
a second voltage at the second conduction terminal; and
connect the selected voltage to a body terminal of the resistance switching transistor.

5. The HV BPS circuit of claim 4 , wherein the body voltage selector circuit is configured to select a highest voltage from the first voltage and the second voltage if the resistance switching transistor is a PMOS transistor.

6. The HV BPS circuit of claim 4 , wherein the body voltage selector circuit is configured to select a lowest voltage from the first voltage and the second voltage if the resistance switching transistor is a NMOS transistor.

7. The HV BPS circuit of claim 1 , wherein the two HV transistors comprise a first HV transistor connected in series with a second HV transistor, wherein an orientation of each of the first HV transistor and the second HV transistor is arranged such that a body diode conduction path of the first HV transistor is in opposite direction to a body diode conduction path of the second HV transistor.

8. The HV BPS circuit of claim 1 , further comprising a first sense resistor connected between the first terminal and the HV block.

9. The HV BPS circuit of claim 1 , further comprising a second sense resistor connected between the second terminal and the resistance network.

10. The HV BPS circuit of claim 1 , wherein the HV block is configured to receive HV control signals for selectively enabling the two HV transistors for selectively enabling the HV BPS circuit.

11. The HV BPS circuit of claim 1 , further comprising a switch control circuit, wherein the switch control circuit is configured to:
receive a HV enable signal from a separate circuit, controller, or software, the HV enable signal indicating whether the HV BPS circuit should be set to an ON state or an OFF state; and
if the HV enable signal indicates the ON state:
output HV control signals for selectively enabling the two HV transistors; and
output the switching signals as complementary switching signals to the first source switch and the second source switch of each switchable resistance module; or

if the HV enable signal indicates the OFF state:
output HV control signals for selectively disabling the two HV transistors; and
output the switching signals as disabling signals to disable both the first source switch and the second source switch of each switchable resistance module.

12. The HV BPS circuit of claim 11 , wherein the switch control circuit is configured to:
receive the HV enable signal indicating that the HV BPS circuit should be set to an ON state;
output the complementary switching signals to each switchable resistance module at a first time; and
output the HV control signals to enable the two HV transistors at a second time, wherein the second time is delayed with respect to the first time.

13. The HV BPS circuit of claim 11 , wherein the switch control circuit is configured to:
receive the HV enable signal indicating that the HV BPS circuit should be set to an OFF state;
output the HV control signals to disable the two HV transistors at a third time; and
output the disabling switching signals to each switchable resistance module at a fourth time, wherein the fourth time is delayed with respect to the third time.

14. The HV BPS circuit of claim 11 , wherein the switch control circuit is configured to:
receive a required resistance signal from a separate circuit, controller or software, the required resistance signal indicating a required resistance value of the resistance network; and
provide the complementary switching signals to the first source switch and the second source switch of each switchable resistance module based on a required resistance value of the required resistance signal in the HV BPS ON state.

15. The HV BPS circuit of claim 1 , wherein the resistance switching transistor of each switchable resistance module is a low voltage, LV, transistor.

16. The HV BPS circuit of claim 1 , wherein:
the positive voltage supply terminal comprises a positive HV supply terminal; and
the negative voltage supply terminal comprises a negative HV supply terminal.

17. The HV BPS circuit of claim 1 , wherein, for each switchable resistance module, the first biasing resistor and the second biasing resistor comprise the same resistance value.

18. An integrated circuit comprising the HV BPS circuit of claim 1 .

Assignees

• Nxp Usa Inc

Inventors

• Paladugu Ranga Seshu
• Lim Soon G
• Trivedi Ronak Prakashchandra
• Morello Carmelo

Classifications

• H03K17/687

  the devices being field-effect transistors · CPC title

• H03K17/102 Primary

  in field-effect transistor switches · CPC title

• H03K2217/0054

  Gating switches, e.g. pass gates · CPC title

• H03K2217/0018

  Special modifications or use of the back gate voltage of a FET · CPC title

• H03K17/6871

  the output circuit comprising more than one controlled field-effect transistor · CPC title