Method and wafer processing furnace for forming an epitaxial stack of semiconductor epitaxial layers on a plurality of substrates

Patent metadata

Field	Value
Publication number	US-12387930-B2
Application number	US-202318153282-A
Country	US
Kind code	B2
Filing date	Jan 11, 2023
Priority date	Jan 13, 2022
Publication date	Aug 12, 2025
Grant date	Aug 12, 2025

Abstract

A method and a wafer processing furnace for forming an epitaxial stack on a plurality of substrates is provided. In a preferred embodiment, the method comprises providing plurality of substrates to a process chamber. A plurality of deposition cycles are executed, thereby forming the epitaxial stack on the plurality of substrates. The epitaxial comprises a plurality of epitaxial pairs, each pair comprising a first epitaxial layer and a second epitaxial layer. The deposition cycle comprises a first deposition pulse and a second deposition pulse. The first deposition pulse comprises a provision of a first reaction gas mixture to the process chamber, thereby forming the first epitaxial layer and the second deposition pulse comprises a provision of a second reaction gas mixture to the process chamber, thereby forming the second epitaxial layer.

First claim

The invention claimed is:

1. A method of forming an epitaxial stack on a plurality of substrates; the method comprising
providing the plurality of substrates to a process chamber;
executing a plurality of deposition cycles, thereby forming the epitaxial stack on the plurality of substrates, the epitaxial stack comprising a plurality of epitaxial pairs, wherein the epitaxial pairs each comprise a first epitaxial layer and a second epitaxial layer, the second epitaxial layer being different from the first epitaxial layer, wherein a deposition cycle comprises:
a first deposition pulse comprising a provision of a first reaction gas mixture to the process chamber, thereby forming the first epitaxial layer; and
a second deposition pulse comprising a provision of a second reaction gas mixture to the process chamber, the second reaction gas mixture being different from the first reaction gas mixture, thereby forming the second epitaxial layer,
wherein the first deposition pulse is carried out at a first deposition temperature;
wherein the second deposition pulse is carried out at a second deposition temperature;
wherein the first deposition temperature is different from the second deposition temperature by at most 50° C.; and
wherein the forming of the first epitaxial layer comprises forming the first epitaxial layer on both sides of the plurality of substrates.

2. The method according to claim 1 , wherein:
the first epitaxial layer comprises a first semiconductor material;
the provision of the first reaction gas mixture comprises providing first semiconductor material precursors;
the second epitaxial layer comprises a second semiconductor material being different than the first semiconductor material; and
the provision of the second reaction gas mixture comprises providing a second semiconductor material precursor.

3. The method according to claim 2 , wherein the first semiconductor material precursors comprise a germanium-containing compound and a first silicon-containing compound; and
wherein the second semiconductor material precursor comprises substantially a second silicon-containing compound.

4. The method according to claim 3 , wherein the germanium-containing compound comprised in the first semiconductor material precursors is at least one of GeH4 and GeCl4.

5. The method according to claim 3 , wherein the second silicon-containing compound comprised substantially in the second semiconductor material precursor is trisilane.

6. The method according to claim 5 , wherein the first silicon-containing compound comprised in the first semiconductor material precursors is trisilane.

7. The method according to claim 3 , wherein the first silicon-containing compound comprised in the first semiconductor material precursors is a cyclic silane or a high order branched silane; and
wherein the germanium-containing compound comprised in the first semiconductor material precursors is GeH4.

8. The method according to claim 7 , wherein the cyclic silane is cyclohexasilane.

9. The method according to claim 7 , wherein the high order branched silane is neopentasilane.

10. The method according to claim 1 , wherein both the first and the second deposition temperature is at a temperature in a range of 300° C.° to 550° C.

11. The method according to claim 5 , wherein the first silicon-containing compound is provided in a continuous flow; and
wherein the germanium-containing compound is provided intermittently.

12. The method according to claim 5 , wherein the germanium-containing compound comprised in the first semiconductor material precursors is GeH4; and
wherein the first silicon-containing compound comprised in the first semiconductor material precursors is mono silane.

13. The method according to claim 1 , wherein the method further comprises, before executing the plurality of deposition cycles, performing a pre-cleaning step, the pre-cleaning step comprising subjecting both the sides of the plurality of substrates to an ambient comprising a fluorine-containing compound.

14. The method according to claim 13 , further comprising subjecting the plurality of substrates to a Cl comprising ambient at a temperature in a range of 400° C.-600° C. after subjecting both the sides of the plurality of substrates to the ambient comprising the fluorine-containing compound.

15. The method according to claim 1 , wherein at least one of the first reaction gas mixture and the second reaction gas mixture comprises an etchant gas.

16. The method according to claim 1 , wherein the process chamber is comprised in a vertical furnace.

Assignees

• Asm Ip Holding Bv

Inventors

• Pierreux Dieter
• Houben Kelly
• Van Aerde Steven
• Verweij Wilco
• Jongbloed Bert
• Dezelah Charles

Classifications

• H10P14/3602

  In-situ cleaning · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/24 Primary

  using chemical vapour deposition [CVD] · CPC title

• H10P14/3252

  Alternating layers, e.g. superlattice · CPC title

• H10P14/3211

  Silicon, silicon germanium or germanium · CPC title