Composable infrastructure enabled by heterogeneous architecture, delivered by CXL based cached switch SOC and extensible via cxloverethernet (COE) protocols

Patent metadata

Field	Value
Publication number	US-12386751-B2
Application number	US-202217809484-A
Country	US
Kind code	B2
Filing date	Jun 28, 2022
Priority date	Jul 18, 2021
Publication date	Aug 12, 2025
Grant date	Aug 12, 2025

Abstract

Described herein are systems, methods, and products utilizing a cache coherent switch on chip. The cache coherent switch on chip may utilize Compute Express Link (CXL) interconnect open standard and allow for multi-host access and the sharing of resources. The cache coherent switch on chip provides for resource sharing between components while independent of a system processor, removing the system processor as a bottleneck. Cache coherent switch on chip may further allow for cache coherency between various different components. Thus, for example, memories, accelerators, and/or other components within the disclose systems may each maintain caches, and the systems and techniques described herein allow for cache coherency between the different components of the system with minimal latency.

First claim

The invention claimed is:

1. A system comprising:
a first server device comprising:
a processor;
a first accelerator, separate from the processor, and configured to accelerate one or more types of workloads;
a second accelerator, separate from the processor, and configured to accelerate the one or more types of workloads;
a first cache coherent switch on chip, communicatively coupled to the first accelerator and the second accelerator via a Compute Express Link (CXL) protocol, wherein the first cache coherent switch on chip is configured to bypass the processor to provide cache coherency between the first accelerator and the second accelerator; and
wherein the first cache coherent switch comprises one or more cache hierarchies, the one or more cache hierarchies indicating a priority for the one or more caches coupled to the first cache coherent switch.

2. The system of claim 1 , further comprising:
a third accelerator, wherein the first cache coherent switch on chip is further configured to provide cache coherency between first accelerator, the second accelerator, and the third accelerator.

3. The system of claim 1 , further comprising:
a first network interface card, communicatively coupled to the first cache coherent switch on chip and to a network.

4. The system of claim 3 , wherein the first network interface card is configured to:
receive, from the network, cache coherent data; and
provide, to the first cache coherent switch on chip, the cache coherent data.

5. The system of claim 3 , further comprising:
a second server device comprising:
a third accelerator;
a second cache coherent switch on chip, communicatively coupled to the third accelerator and configured to:
receive, from a second network interface card, the cache coherent data; and
provide, to the third accelerator, the cache coherent data; and
the second network interface card, communicatively coupled to the second cache coherent switch on chip and to the first network interface card via the network, wherein the first cache coherent switch on chip and the second cache coherent switch on chip are configured to provide cache coherency between the first accelerator, the second accelerator, and the third accelerator by:
receiving cache coherent data from the first accelerator;
providing the cache coherent data to the second accelerator; and

providing the cache coherent data to the first network interface card for communication to the second cache coherent switch on chip via the network and the second network interface card.

6. The system of claim 1 , further comprising a memory, wherein the first cache coherent switch on chip is further configured to provide cache coherency to the memory.

7. The system of claim 1 , wherein the first cache coherent switch on chip comprises a microprocessor, and wherein the microprocessor is configured to direct cache coherent data to the first accelerator and/or the second accelerator to provide the cache coherency.

8. A method comprising:
receiving, with a cache coherent switch on chip from a network interface card, cache coherent data addressed to a first accelerator, the cache coherent switch comprising one or more cache hierarchies, the one or more cache hierarchies indicating a priority for the one or more caches coupled to the first cache coherent switch;
providing, by the cache coherent switch on chip to the first accelerator while bypassing the processor, the cache coherent data;
receiving, with the cache coherent switch on chip from the first accelerator, a bias change;
providing, by the cache coherent switch on chip to a processor, the bias change;
receiving, with the cache coherent switch on chip from the processor, line resolved data; and
providing, by the cache coherent switch on chip to the first accelerator, the line resolved data to cause the first accelerator to write the cache coherent data into a cache coherent memory of a second accelerator;
wherein the first accelerator and the second accelerator, separate from the processor, are configured to accelerate one or more types of workloads.

9. The method of claim 8 , further comprising:
receiving, with the cache coherent switch on chip from the processor, snoop data; and
providing, by the cache coherent switch on chip to a first snooping component, the snoop data, wherein the snoop data indicates the first snooping component.

10. The method of claim 9 , wherein the first snooping component is the second accelerator.

Assignees

• Avago Tech Int Sales Pte Lid

Inventors

• Shah Shreyas
• Apostol Jr George
• Subramaniyan Nagarajan
• Regula Jack
• Earl Jeffrey S

Classifications

• G06F12/0837

  with software control, e.g. non-cacheable data · CPC title

• G06F12/0646

  Configuration or reconfiguration · CPC title

• G06F13/1673

  using buffers · CPC title

• G06F12/1466

  Key-lock mechanism · CPC title

• G06N20/00

  Machine learning · CPC title