Multi-buffered register files with shared access circuits

Patent metadata

Field	Value
Publication number	US-12386618-B2
Application number	US-202017132895-A
Country	US
Kind code	B2
Filing date	Dec 23, 2020
Priority date	Dec 23, 2020
Publication date	Aug 12, 2025
Grant date	Aug 12, 2025

Abstract

Systems, apparatuses and methods identify a plurality of registers that are associated with a system-on-chip. The plurality of registers includes a first portion dedicated to write operations and a second portion dedicated to read operations. The technology writes data to the first portion of the plurality of registers, and transfers the data from the first portion to the second portion.

First claim

We claim:

1. A computing system comprising:
a system-on-chip that includes a plurality of registers, and access circuitry to access the plurality of registers, wherein the plurality of registers includes a first portion dedicated to write operations and a second portion dedicated to read operations; and
a memory including a set of executable program instructions, which when executed by the system-on-chip, cause the computing system to:
write data to the first portion of the plurality of registers as part of the write operations;
control the write operations for writing data into the first portion based on a first clock signal;
control the read operations for reading data from the second portion based on the first clock signal; and
control data transfer from the first portion to the second portion based on a second clock signal, wherein the second clock signal is different from the first clock signal.

2. The computing system of claim 1 , wherein the instructions, when executed, further cause the computing system to execute the data transfer from the first portion to the second portion in response to a pulse of the second clock signal being identified.

3. The computing system of claim 2 , wherein the instructions, when executed, further cause the computing system to:
write the data to the first portion by writing the data to the first portion during one or more first close cycles of the first clock signal prior to the pulse of the second clock signal being identified.

4. The computing system of claim 3 , wherein the instructions, when executed, further cause the computing system to:
read, as part of the read operations, the data in the second portion during one or more clock cycles of the first clock signal after the pulse is identified.

5. The computing system of claim 1 , wherein the plurality of registers is to include:
a first register that is to be associated with input features associated with a neural network,
a second register that is to be associated with filters associated with the neural network, and
a third register that is to be associated with output features associated with the neural network.

6. The computing system of claim 1 , wherein the instructions, when executed, further cause the computing system to:
in each of a plurality of consecutive clock cycles of the first clock signal, retrieve further data from a storage and store the retrieved further data in the first portion.

7. The computing system of claim 1 , wherein the instructions, when executed, further cause the computing system to:
in each of a plurality of consecutive clock cycles of the first clock signal, read further data from the second portion as part of the read operations.

8. A semiconductor apparatus comprising:
one or more substrates; and
logic coupled to the one or more substrates, wherein the logic is implemented in one or more of configurable logic or fixed-functionality logic hardware, the logic coupled to the one or more substrates to:
identify a plurality of registers that is associated with a system-on-chip, wherein the plurality of registers include a first portion dedicated to write operations and a second portion dedicated to read operations;
write data to the first portion of plurality of registers as part of the write operations;
control the write operations for writing data into the first portion based on a first clock signal;
control the read operations for reading data from the second portion based on the first clock signal; and
control data transfer from the first portion to the second portion based on a second clock signal, wherein the second clock signal is different from the first clock signal.

9. The apparatus of claim 8 , wherein the logic coupled to the one or more substrates is further to:
execute the data transfer from the first portion to the second portion in response to a pulse of the second clock signal being identified.

10. The apparatus of claim 9 , wherein the logic coupled to the one or more substrates is to:
write the data to the first portion by writing the data to the first portion during one or more first close cycles of the first clock signal prior to the pulse of the second clock signal being identified.

11. The apparatus of claim 10 , wherein the logic coupled to the one or more substrates is to:
read, as part of the read operations, the data in the second portion during one or more clock cycles of the first clock signal after the pulse is identified.

12. The apparatus of claim 8 , where in the plurality of registers is to include:
a first register that is to be associated with the input features associated with a neural network,
a second register that is to be associated with filters associated with the neural network, and
a third register that is to be associated with output features associated with the neural network.

13. The apparatus of claim 8 , wherein the logic coupled to the one or more substrates is to:
in each of a plurality of consecutive clock cycles of the first clock signal, retrieve further data from a storage and store the retrieved further data in the first place.

14. The apparatus of claim 8 , wherein the logic coupled to the one or more substrates is to:
in each of a plurality of consecutive clock cycles of the first clock signal, read further data from the second portion as part of the read operations.

15. The apparatus of claim 8 , wherein the logic coupled to the one or more substrates includes transistor channel regions that are positioned within one or more substrates.

16. A method comprising:
identifying a plurality of registers that are associated with a system-on-chip, wherein the plurality of registers includes a first portion dedicated to write operations and a second portion dedicated to read operations;
writing data to the first portion of the plurality of registers as part of the write operations;
controlling the write operations for writing data into the first portion based on a first clock signal;
controlling the read operations for reading data from the second portion based on the first clock signal; and
controlling data transfer from the first portion to the second portion based on a second clock signal, wherein the second clock signal is different from the first clock signal.

17. The method of claim 16 , further comprising:
executing the data transfer from the first portion to the second portion in a response to a pulse of the second clock signal being identified.

18. The method of claim 17 , wherein writing the data to the first portion comprises writing the data to the first portion during one or more first clock cycles of the first clock signal prior to the pulse of the second clock signal being identified.

19. The method of claim 18 , further comprising:
reading, as part of the read operations, the data in the second portion during one or more clock cycles of the first clock signal after the pulse is identified.

20. The method of claim 16 , wherein the plurality of registers includes:
a first register associated with input features associated with a neural network,
a second register associated with filters associated with a neural network, and
a third register associated with output features associated with the neural network.

21. The method of claim 16 , further comprising:
in each of a plurality of consecutive clock cycles of the first clock signal, retrieving further data from a storage and storing is retrieved further data in the first portion.

Assignees

• Intel Corp

Inventors

• Hsu Steven
• Agarwal Amit
• Mohapatra Debabrata
• Raha Arnab
• Jung Moongon
• Chinya Gautham
• Krishnamurthy Ram

Classifications

• G06F9/30141

  Implementation provisions of register files, e.g. ports · CPC title

• G06F9/3013

  according to data content, e.g. floating-point registers, address registers · CPC title

• G06F9/3012

  Organisation of register space, e.g. banked or distributed register file · CPC title

• G06F13/1689 Primary

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title

• G06F15/7807

  System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package · CPC title