Tagged memory operated at lower VMIN in error tolerant system

Patent metadata

Field	Value
Publication number	US-12386506-B2
Application number	US-202318488581-A
Country	US
Kind code	B2
Filing date	Oct 17, 2023
Priority date	Sep 9, 2019
Publication date	Aug 12, 2025
Grant date	Aug 12, 2025

Abstract

A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.

First claim

The invention claimed is:

1. A method of implementing an artificial neural network, the method comprising:
initiating performance of a process using a first subset of memory cells of a set of a memory cells of a memory array to store data at a first operational voltage that corresponds to a first operational accuracy of the process, wherein the set of memory cells of the memory array are arranged as a plurality of rows of memory cells intersecting a plurality of columns of memory cells and the first subset of memory cells includes a subset of columns in the plurality of columns of memory cells, a subset of rows in the plurality of rows of memory cells, or both a subset of columns in the plurality of columns of memory cells and a subset of rows in the plurality of rows of memory cells;
detecting an event associated with the process, wherein the event is a transition from processing associated with a first layer of the artificial neural network to processing associated with a second layer of the artificial neural network; and
in response to detection of the event, modifying the performance of the process to correspond to a second operational accuracy that is higher than the first operational accuracy, wherein the modifying the performance of the process includes:
providing, to the first subset of memory cells, a second operational voltage that is higher than the first operational voltage; or
initiating performance of the process using a second subset of memory cells of the set of memory cells of the memory array to store data at a third operational voltage that corresponds to the second operational accuracy of the process.

2. The method of claim 1 , wherein modifying the performance of the process includes:
providing, to the first subset of memory cells, the second operational voltage that is higher than the first operational voltage.

3. The method of claim 1 , wherein modifying the performance of the process includes:
initiating performance of the process using the second subset of memory cells of the set of memory cells of the memory array to store data at the third operational voltage that corresponds to the second operational accuracy of the process.

4. The method of claim 1 , wherein second and third operational voltages are higher than the first operational voltage.

5. The method of claim 1 , wherein modifying the performance of the process includes:
initiating performance of a second process using the plurality of memory cells to store data at the first operational accuracy.

6. The method of claim 1 , comprising:
simultaneously providing different operational voltages to the first and second subsets of memory cells of the memory array.

7. A non-transitory computer-readable medium having contents that cause a processing device to perform a method of implementing an artificial neural network, the method comprising:
initiating performance of a process using a first subset of memory cells of set of memory cells of a memory array to store data at a first operational voltage that corresponds to a first operational accuracy of the process, wherein the set of memory cells of the memory array are arranged as a plurality of rows of memory cells intersecting a plurality of columns of memory cells and the first subset of memory cells includes a subset of columns in the plurality of columns of memory cells, a subset of rows in the plurality of rows of memory cells, or both a subset of columns in the plurality of columns of memory cells and a subset of rows in the plurality of rows of memory cells;
detecting an event associated with the process, wherein the event is a transition from processing associated with a first layer of the artificial neural network to processing associated with a second layer of the artificial neural network; and
in response to detection of the event, modifying the performance of the process to correspond to a second operational accuracy that is higher than the first operational accuracy, wherein the modifying the performance of the process includes:
providing, to the first subset of memory cells, a second operational voltage that is higher than the first operational voltage; or
initiating performance of the process using a second subset of memory cells of the set of memory cells of the memory array to store data at a third operational voltage that corresponds to the second operational accuracy of the process.

8. The non-transitory computer-readable medium of claim 7 , wherein modifying the performance of the process includes:
providing, to the first subset of memory cells, the second operational voltage that is higher than the first operational voltage.

9. The non-transitory computer-readable medium of claim 7 , wherein modifying the performance of the process includes:
initiating performance of the process using the second subset of memory cells of the set of memory cells of the memory array to store data at the third operational voltage that corresponds to the second operational accuracy of the process.

10. The non-transitory computer-readable medium of claim 7 , wherein second and third operational voltages are higher than the first operational voltage.

11. The non-transitory computer-readable medium of claim 7 , wherein modifying the performance of the process includes:
initiating performance of a second process using the plurality of memory cells to store data at the first operational accuracy.

12. The non-transitory computer-readable medium of claim 7 , wherein the contents comprise instructions executed by the processing device.

13. A device, comprising:
a memory array arranged as a plurality of rows of memory cells intersecting a plurality of columns of memory cells, wherein the memory cells, in operation, store data; and
processing circuitry coupled to the memory array, wherein the processing circuitry, in operation, implements an artificial neural network, the implementing the artificial neural network including:
initiating performance of a process using a first subset of memory cells of the memory to store data at a first operational voltage that corresponds to a first operational accuracy of the process, wherein the first subset of memory cells includes a subset of columns in the plurality of columns of memory cells, a subset of rows in the plurality of rows of memory cells, or both a subset of columns in the plurality of columns of memory cells and a subset of rows in the plurality of rows of memory cells;
detecting an event associated with the process, wherein the event is a transition from processing associated with a first layer of the artificial neural network to processing associated with a second layer of the artificial neural network; and
in response to detection of the event, modifying the performance of the process to correspond to a second operational accuracy that is higher than the first operational accuracy, wherein the modifying the performance of the process includes:
providing, to the first subset of memory cells, a second operational voltage that is higher than the first operational voltage; or
initiating performance of the process using a second subset of memory cells of the memory array to store data at a third operational voltage that corresponds to the second operational accuracy of the process.

14. The device of claim 13 , wherein modifying the performance of the process includes:
providing, to the first subset of memory cells, the second operational voltage that is higher than the first operational voltage.

15. The device of claim 13 , wherein modifying the performance of the process includes:
initiating performance of the process

Assignees

• St Microelectronics Srl
• St Microelectronics Int Nv

Inventors

• Chawla Nitin
• Desoli Giuseppe
• Grover Anuj
• Boesch Thomas
• Singh Surinder Pal
• Ayodhyawasi Manuj

Classifications

• G06N3/0464

  Convolutional networks [CNN, ConvNet] · CPC title

• G06N3/08

  Learning methods · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0655

  Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title