Display substrate and manufacturing method therefor, and display apparatus

US12382806B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12382806-B2
Application numberUS-202117915678-A
CountryUS
Kind codeB2
Filing dateSep 3, 2021
Priority dateOct 22, 2020
Publication dateAug 5, 2025
Grant dateAug 5, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A display substrate includes a flexible substrate, a cathode layer located on a first side of the flexible substrate and at least one insulating layer located between the flexible substrate and the cathode layer. The flexible substrate includes at least one stretchable region, the stretchable region extends from the display area to the non-display area, and the stretchable region is provided with a plurality of holes arranged in an array therein. A border of the cathode layer is located in the non-display area. The at least one insulating layer is configured to expose the plurality of holes, the at least one insulating layer is provided with at least one partition groove therein, an orthographic projection of a partition groove on the flexible substrate is disposed around a hole of the plurality of holes, and the partition groove is configured to partition the cathode layer.

First claim

Opening claim text (preview).

What is claimed is: 1. A display substrate having a display area and a non-display area adjacent to the display area; the display substrate comprising: a flexible substrate, the flexible substrate including at least one stretchable region, the stretchable region extending from the display area to the non-display area, and the stretchable region being provided with a plurality of holes arranged in an array therein; a cathode layer located on a first side of the flexible substrate, the cathode layer extending from the display area to the non-display area, and a border of the cathode layer being located in the non-display area; and at least one insulating layer located between the flexible substrate and the cathode layer, the at least one insulating layer being configured to expose the plurality of holes; wherein the at least one insulating layer is provided with at least one partition groove therein, an orthographic projection of a partition groove on the flexible substrate is disposed around a hole of the plurality of holes, and the partition groove is configured to partition the cathode layer. 2. The display substrate according to claim 1 , further comprising: a light-emitting functional layer located between the cathode layer and the at least one insulating layer; the light-emitting functional layer extending from the display area to the non-display area, and a border of the light-emitting functional layer being located between the border of the cathode layer and a border of the display area; wherein the at least one partition groove includes partition grooves, and at least a part of the partition grooves each partition both of the cathode layer and the light-emitting functional layer. 3. The display substrate according to claim 1 , wherein a section obtained by sectioning the partition groove with a plane parallel to both of a radial direction of the hole and a thickness direction of the display substrate is substantially in a shape of an inverted “T”. 4. The display substrate according to claim 1 , wherein the at least one insulating layer includes a first inorganic insulating layer and a first organic insulating layer that are sequentially away from the cathode layer; and the partition groove passes through the first inorganic insulating layer and at least a portion of the first organic insulating layer. 5. The display substrate according to claim 1 , further comprising: at least one signal line disposed on the first side of the flexible substrate and located in the non-display area; a signal line having at least one first avoidance opening, and a first avoidance opening being configured to expose the hole; wherein the at least one insulating layer covers a sidewall of the first avoidance opening; or the at least one insulating layer covers the sidewall of the first avoidance opening and a portion, proximate to the first avoidance opening, of a surface of the signal line away from the flexible substrate. 6. The display substrate according to claim 5 , wherein the signal line includes a first metal layer and a second metal layer that are sequentially away from the flexible substrate; the at least one insulating layer includes a first organic insulating layer and a second organic insulating layer that are sequentially proximate to the flexible substrate; the second organic insulating layer covers a side of the first metal layer proximate to the hole and a portion of a surface of the first metal layer away from the flexible substrate; the second metal layer is in electrical contact with the first metal layer, and the second metal layer covers a side of the second organic insulating layer away from the hole and a portion of a surface of the second organic insulating layer away from the flexible substrate; and the first organic insulating layer covers a side of the second metal layer proximate to the hole and a portion of a surface of the second metal layer away from the flexible substrate. 7. The display substrate according to claim 6 , wherein the at least one insulating layer further includes a first inorganic insulating layer and a second inorganic insulating layer; a portion of the second inorganic insulating layer is located between the second organic insulating layer and the flexible substrate, another portion of the second inorganic insulating layer is located between the first metal layer and the second metal layer, and yet another portion of the second inorganic insulating layer is located between the first metal layer and the second organic insulating layer; and the first inorganic insulating layer covers at least a portion of a surface of the first organic insulating layer away from the flexible substrate, a side of the first organic insulating layer proximate to the hole and a side of the second organic insulating layer proximate to the hole, and the first inorganic insulating layer is in contact with to the second inorganic insulating layer. 8. The display substrate according to claim 5 , wherein the signal line is a voltage signal line, and the voltage signal line is disposed around the display area; the display substrate further comprises: a cathode lapping layer located in the non-display area, the cathode lapping layer including a first portion and a second portion connected to each other, the first portion being electrically connected to a surface of the cathode layer proximate to the flexible substrate, and the second portion being connected to a surface of the voltage signal line away from the flexible substrate; the cathode lapping layer having at least one second avoidance opening, and a second avoidance opening being configured to expose the hole; wherein the at least one insulating layer covers a sidewall of the second avoidance opening; or the at least one insulating layer covers the sidewall of the second avoidance opening and a portion, proximate to the second avoidance opening, of a surface of the cathode lapping layer away from the flexible substrate. 9. The display substrate according to claim 8 , further comprising: a first blocking dam disposed on the first side of the flexible substrate, the first blocking dam being located in the non-display area and disposed around the display area; wherein the first blocking dam covers at least a side of the voltage signal line away from the display area and a side of the cathode lapping layer away from the display area; the first blocking dam has at least one third avoidance opening, and a third avoidance opening is configured to expose another hole of the plurality of holes; a second blocking dam disposed on the first side of the flexible substrate, the second blocking dam being located in the non-display area and disposed around the display area; wherein the second blocking dam is located on a surface of the second portion of the cathode lapping layer away from the flexible substrate; the second blocking dam has at least one fourth avoidance opening, and a fourth avoidance opening is configured to expose the hole exposed by the second avoidance opening, the first avoidance opening and the second avoidance opening; and an encapsulation layer disposed on the first side of the flexible substrate; the encapsulation layer covering the cathode layer, the first blocking dam and the second blocking dam; wherein the encapsulation layer has at least one fifth avoidance opening, and a fifth avoidance opening is configured to expose a corresponding hole of the plurality of the holes. 10. The display substrate according to claim 1 , wherein the display substrate is in a shape of a rectangle, a number of stretchable regions is four, and the four stretchable regions are respectively located at four corners of the display substrate.

Assignees

Inventors

Classifications

  • H10K77/111Primary

    Flexible substrates · CPC title

  • Encapsulations · CPC title

  • characterised by their shape · CPC title

  • Manufacture or treatment · CPC title

  • Manufacturing or production processes characterised by the final manufactured product · CPC title

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Frequently asked questions

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What does patent US12382806B2 cover?
A display substrate includes a flexible substrate, a cathode layer located on a first side of the flexible substrate and at least one insulating layer located between the flexible substrate and the cathode layer. The flexible substrate includes at least one stretchable region, the stretchable region extends from the display area to the non-display area, and the stretchable region is provided wi…
Who is the assignee on this patent?
Boe Technology Group Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10K77/111. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 05 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 7 related publications on this page (citations in our corpus or others sharing the same primary CPC).