Display substrate with multiple signal lines arranged in one shift register unit and display device

Patent metadata

Field	Value
Publication number	US-12382805-B2
Application number	US-202318682189-A
Country	US
Kind code	B2
Filing date	Jan 31, 2023
Priority date	Dec 3, 2021
Publication date	Aug 5, 2025
Grant date	Aug 5, 2025

Abstract

A display substrate includes a base substrate including a display area and a peripheral area on at least one side of the display area; a pixel array, located in the display area and including multiple pixel units; and, a scan driving module, located in a driving circuit area of the peripheral area, and including multiple shift register units, multiple signal lines being arranged in one shift register units, and extending along a first direction; wherein a ratio of a sum W1 of widths of the multiple signal lines in a second direction to a width W2 of the shift register unit in the second direction is W1/W2, and a length of at least one pixel unit along the first direction is a pixel pitch value; the first direction intersects the second direction; a product of W1/W2 and the pixel pitch value is greater than 18 um and less than 40 um.

First claim

What is claimed is:

1. A display substrate, comprising:
a base substrate including a display area and a peripheral area located on at least one side of the display area;
a pixel array, located in the display area and including a plurality of pixel units; and,
a scan driving module, located in a driving circuit area of the peripheral area, and including a plurality of shift register units, a plurality of signal lines being arranged in one shift register unit of the plurality of shift register units, and the plurality of signal lines extending along a first direction;
wherein a ratio of a sum W1 of widths of the plurality of signal lines in a second direction to a width W2 of the shift register unit in the second direction is W1/W2, and a length of at least one pixel unit along the first direction is a pixel pitch value; the first direction intersects the second direction;
a product of W1/W2 and the pixel pitch value is greater than 18 um and less than 40 um.

2. The display substrate according to claim 1 , wherein the plurality of signal lines include all signal lines in the shift register unit.

3. The display substrate according to claim 1 , wherein the plurality of signal lines include all signal lines overlapping an orthographic projection of the shift register unit on the base substrate.

4. The display substrate according to claim 1 , wherein W1/W2 is greater than 0.4 and less than 0.7.

5. The display substrate according to claim 1 , wherein a product of W1/W2 and the pixel pitch value is greater than 27 um and less than 36 um;
or
the product of W1/W2 and the pixel pitch value is greater than 18 um and less than or equal to 27 um;
or
the product of W1/W2 and the pixel pitch value is greater than or equal to 36 um and less than 40 um;
or
the product of W1/W2 and the pixel pitch value is greater than 29 um and less than 35 um.

6. The display substrate according to claim 1 , wherein the display substrate comprises a first conductive layer, an insulating layer, and a second conductive layer, and the insulating layer is arranged between the first conductive layer and the second conductive layer;
at least one signal line of the plurality of signal lines is arranged on the first conductive layer, and at least one signal line of the plurality of signal lines is arranged on the second conductive layer.

7. The display substrate according to claim 1 , wherein the shift register unit includes at least one transistor arranged in the driving circuit area, a first electrode of the transistor, a second electrode of the transistor and the plurality of signals lines are arranged on a same layer;
or
wherein the shift register unit includes at least one transistor arranged in the driving circuit area, a first electrode of the transistor and a second electrode of the transistor are arranged on a same layer, and the plurality of signal lines and the first electrode of the transistor are arranged at different layers.

8. The display substrate according to claim 1 , wherein the shift register unit includes at least one signal line arranged in the driving circuit area, the at least one signal line is configured to provide a DC power signal;
a ratio W3/W2 of a width W3 of the at least one signal line in the second direction to the width W2 of the shift register unit in the second direction is greater than or equal to 0.15;
or
the ratio W3/W2 of the width W3 of the at least one signal line in the second direction to the width W2 of the shift register unit in the second direction is greater than or equal to 0.3.

9. The display substrate according to claim 1 , wherein the shift register unit comprises at least one signal line arranged in the driving circuit area, the at least one signal line is configured to provide a clock signal;
a ratio W4/W2 of a width W4 of the at least one signal line in the second direction to the width W2 of the shift register unit in the second direction is greater than or equal to 0.015;
or
the ratio W4/W2 of the width W4 of the at least one signal line in the second direction to the width W2 of the shift register unit in the second direction is greater than or equal to 0.03.

10. The display substrate according to claim 1 , wherein the shift register unit comprises at least two transistors arranged in the driving circuit area;
active layers of the at least two transistors are formed by a continuous semiconductor layer, and an orthographic projection of one signal line of the plurality of signal lines on the base substrate partially overlaps an orthographic projection of the semiconductor layer on the base substrate.

11. The display substrate according to claim 1 , wherein the shift register unit comprises a fourth transistor, a fifth transistor, an eighth transistor and a thirteenth transistor; a second electrode of the fourth transistor is coupled to a second electrode of the fifth transistor, a second electrode of the eighth transistor, a first electrode of the fifth transistor, and a first electrode of the thirteenth transistor are coupled to each other;
an active layer of the fourth transistor, an active layer of the fifth transistor, an active layer of the thirteenth transistor, and an active layer of the eighth transistor are formed by a continuous first semiconductor layer;
an orthographic projection of the active layer of the fourth transistor on the base substrate, an orthographic projection of the active layer of the fifth transistor on the base substrate, an orthographic projection of the active layer of the eighth transistor on the base substrate and an orthographic projection of a part of the active layer of the thirteenth transistor on the base substrate together form an E-type pattern or an F-type pattern;
the orthographic projection of the active layer of the fourth transistor on the base substrate and the orthographic projection of the active layer of the fifth transistor on the base substrate together form an L-type pattern,
wherein the shift register unit comprises a plurality of signal lines, and the plurality of signal lines comprises a first voltage line;
an orthographic projection of the first voltage line on the base substrate partially overlaps an orthographic projection of the first semiconductor layer on the base substrate;
or
wherein the shift register unit comprises the plurality of signal lines, and the plurality of signal lines comprises a second clock signal line;
an orthographic projection of the second clock signal line on the base substrate partially overlaps the orthographic projection of the first semiconductor layer on the base substrate;
or
wherein a channel of the fourth transistor extends along the second direction, a channel of the fifth transistor extends along the first direction, a channel of the thirteenth transistor extends along the second direction, and a channel of the eighth transistor extends along the first direction.

12. The display substrate according to claim 1 , wherein the shift register unit comprises a second transistor and a third transistor; a second electrode of the second transistor is coupled to a second electrode of the third transistor;
an active layer of the second transistor and an active layer of the third transistor are formed by a continuous fourth semiconductor layer, and an orthographic projection of the active layer of the second transistor on the base substrate and an orthographic projection of the active layer of the third transistor on the base substrate together form an I-type pattern,
wherein a channel of the second transistor extends along the first direction, and a channel of the third transistor extends along the first direction.

13.

Assignees

• Beijing Boe Technology Dev Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Yao Xing
• Hao Xueguang
• Qiao Yong
• Wang Jingquan
• Wu Xinyin

Classifications

• G11C19/287

  Organisation of a multiplicity of shift registers · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G3/3266 Primary

  Details of drivers for scan electrodes · CPC title

• H10K59/1213

  the pixel elements being TFTs · CPC title