Semiconductor device and semiconductor circuit

Patent metadata

Field	Value
Publication number	US-12382648-B2
Application number	US-202418631243-A
Country	US
Kind code	B2
Filing date	Apr 10, 2024
Priority date	Sep 16, 2020
Publication date	Aug 5, 2025
Grant date	Aug 5, 2025

Abstract

A semiconductor device of embodiments includes: a semiconductor layer having a first face and a second face opposite to the first face and including a first trench, a second trench, and a third trench provided on a first face side; a first gate electrode in the first trench; a second gate electrode in the second trench; a third gate electrode in the third trench; a fourth gate electrode and a fifth gate electrode provided on a second face side; a first electrode contacting the first face; a second electrode contacting the second face; a first electrode pad electrically connected to the first gate electrode; a second electrode pad electrically connected to the second gate electrode; a third electrode pad electrically connected to the third gate electrode; a fourth electrode pad electrically connected to the fourth gate electrode; and a fifth electrode pad electrically connected to the fifth gate electrode.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor layer having a first face and a second face opposite to the first face and including a first trench provided in a first face side of the semiconductor layer, a second trench provided in the first face side of the semiconductor layer, and a third trench provided in the first face side of the semiconductor layer;
a first gate electrode provided in the first trench;
a second gate electrode provided in the second trench;
a third gate electrode provided in the third trench;
a fourth gate electrode provided on a second face side of the semiconductor layer;
a fifth gate electrode provided on the second face side of the semiconductor layer;
a first electrode in contact with the first face;
a second electrode in contact with the second face;
a first electrode pad electrically connected to the first gate electrode;
a second electrode pad electrically connected to the second gate electrode;
a third electrode pad electrically connected to the third gate electrode;
a fourth electrode pad electrically connected to the fourth gate electrode; and
a fifth electrode pad electrically connected to the fifth gate electrode,
wherein the semiconductor layer further includes:
a first semiconductor region of a first conductive type;
a second semiconductor region of a second conductive type provided between the first semiconductor region of the first conductive type and the first face, facing the first gate electrode, facing the second gate electrode, and facing the third gate electrode;
a third semiconductor region of a first conductive type provided between the second semiconductor region of the second conductive type and the first face and in contact with the first electrode, the third semiconductor region of the first conductive type being in contact with the first trench, the second trench, and the third trench;
a fourth semiconductor region of a second conductive type provided between the first semiconductor region of the first conductive type and the second face, facing the fourth gate electrode, and in contact with the second electrode;
a fifth semiconductor region of a second conductive type provided between the first semiconductor region of the first conductive type and the second face, facing the fifth gate electrode, and in contact with the second electrode;
a sixth semiconductor region of a first conductive type provided between the fourth semiconductor region of the second conductive type and the second face, and in contact with the second electrode; and
a seventh semiconductor region of a first conductive type provided between the fifth semiconductor region of the second conductive type and the second face, and in contact with the second electrode.

2. A semiconductor circuit, comprising:
the semiconductor device according to claim 1 ; and
a control circuit for controlling a voltage to be applied to the first electrode pad, the second electrode pad, the third electrode pad, the fourth electrode pad, and the fifth electrode pad.

3. The semiconductor circuit according to claim 2 ,
wherein the control circuit is configured to apply a first turn-on voltage to the first electrode pad, to apply a second turn-on voltage to the second electrode pad, and to apply a third turn-on voltage to the third electrode pad,
the control circuit is configured to apply a first turn-off voltage to the third electrode pad, after a first predetermined time passes from the application of the first turn-on voltage to the first electrode pad, the application of the second turn-on voltage to the second electrode pad, and the application of the third turn-on voltage to the third electrode pad,
the control circuit is configured to apply a fourth turn-on voltage to the fifth electrode pad, after a second predetermined time passes from the application of the first turn-off voltage to the third electrode pad, and
the control circuit is configured to apply a fifth turn-on voltage to the fourth electrode pad, after a third predetermined time passes from the application of the fourth turn-on voltage to the fifth electrode pad.

4. The semiconductor circuit according to claim 3 ,
wherein, the control circuit is configured to apply a second turn-off voltage to the first electrode pad, after a fourth predetermined time passes from the application of the first turn-on voltage to the first electrode pad, the application of the second turn-on voltage to the second electrode pad, and the application of the third turn-on voltage to the third electrode pad,
the control circuit is configured to apply a third turn-off voltage to the second electrode pad, after the application of the first turn-off voltage to the third electrode pad and before the application of the second turn-off voltage to the first electrode pad, and
the control circuit is configured to apply the fourth turn-on voltage to the fifth electrode pad, before the application of the second turn-off voltage to the first electrode pad.

5. A semiconductor device, comprising:
a semiconductor layer having a first face and a second face opposite to the first face and including a first trench provided in a first face side of the semiconductor layer, a second trench provided in the first face side of the semiconductor layer, and a third trench provided in the first face side of the semiconductor layer;
a first gate electrode provided in the first trench;
a second gate electrode provided in the second trench;
a third gate electrode provided in the third trench;
a fourth gate electrode provided on a second face side of the semiconductor layer;
a fifth gate electrode provided on the second face side of the semiconductor layer;
a first electrode in contact with the first face;
a second electrode in contact with the second face;
a first electrode pad electrically connected to the first gate electrode;
a second electrode pad electrically connected to the second gate electrode;
a third electrode pad electrically connected to the third gate electrode;
a fourth electrode pad electrically connected to the fourth gate electrode; and
a fifth electrode pad electrically connected to the fifth gate electrode,
wherein the semiconductor layer further includes:
a first semiconductor region of a first conductive type;
a second semiconductor region of a second conductive type provided between the first semiconductor region of the first conductive type and the first face, facing the first gate electrode, facing the second gate electrode, and facing the third gate electrode;
a third semiconductor region of a first conductive type provided between the second semiconductor region of the second conductive type and the first face and in contact with the first electrode, the third semiconductor region of the first conductive type being in contact with the first trench and the third trench, the third semiconductor region and the second trench being spaced from each other, and;
a fourth semiconductor region of a second conductive type provided between the first semiconductor region of the first conductive type and the second face, facing the fourth gate electrode, and in contact with the second electrode;
a fifth semiconductor region of a second conductive type provided between the first semiconductor region of the first conductive type and the second face, facing the fifth gate electrode, and in contact with the second electrode;
a sixth semiconductor region of a first conductive type provided between the fourth semiconductor region of the second conductive type and the second face, and in contact with the second electrode; and
a seventh semiconductor region of a first conductive type provided between the fifth semiconductor region of the second conductive type and the second face, and in contact with the sec

Assignees

• Toshiba Kk
• Toshiba Electronic Devices & Storage Corp

Inventors

• Matsudai Tomoko
• Iwakaji Yoko
• Itokazu Hiroko

Classifications

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D62/107

  Buried supplementary regions, e.g. buried guard rings  (multi-RESURF H10D62/111) · CPC title

• H03K17/567

  Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT · CPC title

• H10D12/481 Primary

  having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs · CPC title

• H10D62/126

  Top-view geometrical layouts of the regions or the junctions · CPC title