Microelectronic devices including a selectively removable cap dielectric material, methods of forming the microelectronic devices, and related systems

Patent metadata

Field	Value
Publication number	US-12382633-B2
Application number	US-202217660767-A
Country	US
Kind code	B2
Filing date	Apr 26, 2022
Priority date	Apr 26, 2022
Publication date	Aug 5, 2025
Grant date	Aug 5, 2025

Abstract

A microelectronic device includes tiers of alternating dielectric and conductive materials, a cap oxide material vertically adjacent to the tiers, and pillars extending vertically through the tiers. The cap oxide material is formulated to exhibit a different etch rate relative to an etch rate of the oxide material of the tiers. Additional microelectronic devices, microelectronic systems, and methods of forming a microelectronic device are also disclosed.

First claim

What is claimed is:

1. A microelectronic device, comprising:
tiers of alternating dielectric materials and conductive materials;
pillars extending vertically through the tiers; and
a cap oxide material vertically adjacent to the tiers, the cap oxide material formulated to exhibit a different etch rate relative to an etch rate of the dielectric materials of the tiers,
first sidewalls of the pillars and second sidewalls of the cap oxide material defining a step change between the cap oxide material and the tiers.

2. The microelectronic device of claim 1 , wherein the cap oxide material directly contacts an uppermost tier of the tiers of alternating dielectric materials and conductive materials.

3. The microelectronic device of claim 2 , wherein the dielectric materials of the tiers comprise a first silicon oxide material and the cap oxide material comprises a second silicon oxide material, the second silicon oxide material exhibiting a different quality than the first silicon oxide material.

4. The microelectronic device of claim 3 , wherein the different quality comprises a different density.

5. The microelectronic device of claim 1 , further comprising: conductive plugs adjacent to the pillars.

6. The microelectronic device of claim 5 , wherein a width of at least one of the conductive plugs is increased relative to a width of the pillars.

7. The microelectronic device of claim 1 , wherein the first sidewalls and the second sidewalls defining the step change are tapered, linearly bowed, or curved.

8. A microelectronic device, comprising:
tiers of alternating dielectric materials and conductive materials;
pillars extending vertically through the tiers;
a cap oxide material over the tiers, sidewalls of the cap oxide material offset from sidewalls of the tiers; and
a conductive plug laterally adjacent to the ca oxide material and the tiers a width of the conductive plug laterally adjacent to the tiers less than a width of the conductive plug laterally adjacent to the cap oxide material.

9. The microelectronic device of claim 8 , wherein the conductive plug has substantially vertical sidewalls.

10. The microelectronic device of claim 8 , wherein the conductive plug has curved sidewalls.

11. A microelectronic system, comprising:
an input device;
an output device;
a processor device operably coupled to the input device and the output device; and
a memory device operably coupled to the processor device, the memory device comprising:
one or more decks comprising tiers of alternating oxide materials and conductive materials;
pillars extending vertically through the one or more decks;
a cap material over the one or more decks, the cap material comprising a different oxide material than the oxide materials of the tiers; and
a plug laterally adjacent to the cap material and overlying the pillars, the plug exhibiting two or more different widths along a height thereof.

12. The microelectronic system of claim 11 , wherein the plug extends through the cap material and into the tiers.

13. The microelectronic system of claim 12 , wherein a width of the plug laterally adjacent to the tiers is less than a width of the plug laterally adjacent to the cap material.

14. The microelectronic system of claim 11 , wherein the memory device comprises a three-dimensional NAND memory device.

15. A method of forming a microelectronic device, comprising:
forming tiers of alternating nitride materials and dielectric materials;
forming a cap oxide material vertically adjacent to the tiers, the cap oxide material formulated to exhibit a different etch rate relative to an etch rate of the dielectric materials of the tiers;
removing a first portion of the cap oxide material to form a patterned cap dielectric material;
removing portions of the tiers exposed through the patterned cap oxide material to form pillar openings in the tiers;
removing a second portion of the cap oxide material without substantially removing the nitride materials and the dielectric materials of the tiers;
forming a channel material and cell film materials in the pillar openings to form pillars extending vertically through the tiers first sidewalls of the pillars and second sidewalls of the ca oxide material defining a step change between the cap oxide material and the tiers;
removing the nitride materials of the tiers to form spaces between the dielectric materials of the tiers; and
forming a conductive material in the spaces to form tiers of alternating dielectric materials and conductive materials.

16. The method of claim 15 , wherein removing a second portion of the cap oxide material without substantially removing the nitride materials and the dielectric materials of the tiers comprises selectively removing portions of a cap oxide material adjacent the tiers.

17. The method of claim 15 , wherein forming tiers of alternating nitride materials and dielectric materials comprises using a first atomic layer deposition (ALD) process to deposit the tiers, and wherein forming a cap oxide material adjacent to the tiers comprises using a second, different ALD process to deposit an oxide material adjacent the tiers.

18. The method of claim 15 , wherein forming tiers of alternating nitride and dielectric materials comprises using an ALD process to deposit the tiers, and wherein forming a cap oxide material adjacent to the tiers comprises using a chemical vapor deposition (CVD) process to deposit an oxide material adjacent the tiers.

19. The method of claim 15 , wherein forming a cap oxide material adjacent to the tiers comprises forming an oxide material having a different oxide density than an oxide material of the dielectric materials of the tiers.

20. The method of claim 15 , wherein forming a cap oxide material adjacent to the tiers comprises forming the cap oxide material to be selectively etchable relative to the dielectric materials of the tiers.

Assignees

• Micron Technology Inc

Inventors

• Speetjens Frank
• Wang Yucheng
• Flynn Brendan
• Hossain S M Istiaque
• John Tom J
• Adams Jeremy

Classifications

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title