Signal delay device with reduced size
US-2024128962-A1 · Apr 18, 2024 · US
US12381545B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12381545-B2 |
| Application number | US-202118554742-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 12, 2021 |
| Priority date | Apr 12, 2021 |
| Publication date | Aug 5, 2025 |
| Grant date | Aug 5, 2025 |
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Official abstract text for this publication.
The present disclosure provides a device for signal delay. The device comprises: a frame of insulation material; multiple signal electrodes provided in the frame and electrically connected to each other in series; an input terminal electrically connected to a first of the multiple signal electrodes and configured to receive an input signal; and an output terminal electrically connected to a second of the multiple signal electrodes and configured to output an output signal that is delayed by the multiple signal electrodes with respect to the input signal, wherein at least one of the multiple signal electrodes is located at a different height than those of other signal electrodes with respect to a surface on which the device is to be mounted.
Opening claim text (preview).
What is claimed is: 1. A device for signal delay, the device comprising: a frame of insulation material; multiple signal electrodes provided in the frame, the multiple signal electrodes comprising: a first signal electrode; and a second signal electrode electrically connected in series with the first signal electrode; an input terminal electrically connected to the first signal electrode and configured to receive an input signal; and an output terminal electrically connected to the second signal electrode and configured to output an output signal that is delayed by the multiple signal electrodes with respect to the input signal, wherein at least one of the multiple signal electrodes is located at a different height than those of other signal electrodes with respect to a surface on which the device is to be mounted, wherein the frame has a first hole extending from a first outer surface of the frame to a second outer surface of the frame which is opposed to the first outer surface, thereby forming a first opening in the first outer surface of the frame and a second opening in the second outer surface of the frame, the frame has a second hole extending from the first outer surface of the frame to the second outer surface of the frame, thereby forming a third opening in the first outer surface of the frame and a fourth opening in the second outer surface of the frame, the first signal electrode is located in the first hole, and the second signal electrode is located in the second hole. 2. The device claim 1 , wherein a third signal electrode is located in a third hole extending from the first outer surface of the frame to the second outer surface of the frame, thereby forming a fifth opening in the first outer surface of the frame and a sixth opening in the second outer surface of the frame, and a fourth signal electrode is located in a fourth hole extending from the first outer surface of the frame to the second outer surface of the frame, thereby forming a seventh opening in the first outer surface of the frame and an eighth opening in the second outer surface of the frame. 3. The device of claim 2 , wherein the first signal electrode is electrically connected to the fourth signal electrode via a first conductive pattern on the second outer surface of the frame, the fourth signal electrode is electrically connected to the third signal electrode via a second conductive pattern on the first outer surface of the frame, and the third signal electrode is electrically connected to the second signal electrode via a third conductive pattern on the second outer surface of the frame. 4. The device of claim 3 , wherein other outer surfaces of the frame than the first and second outer surfaces have a conductive layer disposed thereon. 5. The device of claim 4 , wherein the conductive layer covers the other outer surfaces of the frame completely. 6. The device of claim 4 , wherein the first and second outer surfaces have a conductive layer disposed thereon which is insulated from the conductive patterns. 7. The device of claim 1 , wherein the first signal electrode comprises a conductive pattern located on the inner surface of the first hole. 8. The device of claim 1 , wherein the first signal electrode is electrically connected to the second signal electrode via a conductive pattern on the first outer surface of the frame. 9. The device of claim 1 , wherein there are one or more grooves on at least one of the outer surfaces of the frame other than the first and second outer surface, such that each of the grooves reduces the cross-sectional area between adjacent signal electrodes. 10. The device of claim 9 , wherein at least one of the grooves has a cross section of a circular segment. 11. The device of claim 10 , wherein the at least one of the grooves has a cross section of a semi-circle. 12. The device of claim 1 , wherein the frame has one or more additional holes, and each of the additional holes has an opening on the first outer surface and another opening on the second outer surface, such that each of the additional holes reduces the cross-sectional area between adjacent signal electrodes. 13. The device of claim 1 , further comprising: an impedance matching circuit located on an outer surface of the device and/or in the device and configured to match the impedance of the device with an impedance of a circuit with which the device is to be electrically coupled. 14. The device of claim 1 , wherein the insulation material is ceramic. 15. A power amplifier comprising the device of claim 1 .
Fixed delay · CPC title
Power amplifiers, e.g. Class B amplifiers, Class C amplifiers (H03F3/26 - H03F3/30 take precedence) · CPC title
Layout of the delay element · CPC title
by the use of delay lines or other analogue delay elements · CPC title
by the use of delay lines (H03K5/133 takes precedence) · CPC title
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