Liner-free through-silicon-vias formed by selective metal deposition

Patent metadata

Field	Value
Publication number	US-12381129-B2
Application number	US-202217705458-A
Country	US
Kind code	B2
Filing date	Mar 28, 2022
Priority date	Mar 28, 2022
Publication date	Aug 5, 2025
Grant date	Aug 5, 2025

Abstract

Structures for a through-silicon via and methods of forming a structure for a through-silicon via. The structure includes a substrate having a trench and surfaces that border the trench. The structure further includes a through-silicon via having a layer inside the trench. The layer is in direct contact with the surfaces of the substrate.

First claim

What is claimed is:

1. A structure comprising:
a substrate including a trench and a plurality of surfaces that border the trench; and
a through-silicon via including a layer inside the trench, the layer in direct contact with the plurality of surfaces of the substrate, the layer including a first portion adjoining the plurality of surfaces and a second portion that is positioned inside the first portion, the first portion of the layer having a first average grain size, and the second portion of the layer having a second average grain size that differs from the first average grain size.

2. The structure of claim 1 wherein the second average grain size is greater than the first average grain size.

3. The structure of claim 1 wherein the layer comprises a metal.

4. The structure of claim 1 wherein the layer comprises tungsten.

5. The structure of claim 1 wherein the layer exclusively contains tungsten.

6. The structure of claim 1 wherein the through-silicon via is free of a liner between the layer and the plurality of surfaces of the substrate.

7. The structure of claim 6 wherein the layer comprises tungsten.

8. The structure of claim 6 wherein the layer exclusively contains tungsten.

9. The structure of claim 1 wherein the through-silicon via is a single piece of continuous tungsten.

10. The structure of claim 1 wherein the through-silicon via exclusively includes the layer.

11. The structure of claim 1 wherein the trench includes a sidewall and a bottom, and the plurality of surfaces of the substrate are coextensive with the sidewall and the bottom of the trench.

12. The structure of claim 11 wherein the substrate is a bulk semiconductor substrate comprising single-crystal silicon.

13. The structure of claim 1 wherein the layer is surrounded by the plurality of surfaces of the substrate.

14. The structure of claim 1 wherein the through-silicon via is unitary.

15. The structure of claim 1 wherein the substrate comprises silicon, the layer comprises tungsten, and the plurality of surfaces define respective interfaces between the silicon of the substrate and the tungsten of the layer.

16. A method of forming a through-silicon via, the method comprising:
forming a trench in a substrate, wherein the substrate includes a plurality of surfaces that border the trench; and
forming a layer inside the trench to define the through-silicon via, wherein the layer directly contacts the plurality of surfaces of the substrate,
wherein the layer includes a first portion adjoining the plurality of surfaces, a second portion that is positioned inside the first portion, the first portion of the layer has a first average grain size, and the second portion of the layer has a second average grain size that is differs from the first average grain size.

17. The method of claim 16 wherein the layer comprises tungsten formed by a selective deposition process using tungsten hexafluoride and hydrogen as reactant gases.

18. The method of claim 16 wherein the layer comprises tungsten formed by a substantially selective deposition process using tungsten hexafluoride and hydrogen as reactant gases.

19. The method of claim 16 wherein the layer comprises tungsten that is formed by a deposition process using tungsten hexafluoride and hydrogen as reactant gases, and forming the layer inside the trench to define the through-silicon via comprises:
depositing an outer portion of the layer with a silicon reduction reaction; and
depositing an inner portion of the layer with a hydrogen reduction reaction.

20. The method of claim 16 wherein the second average grain size is greater than the first average grain size.

Assignees

• Globalfoundries Us Inc

Inventors

• Thomas David
• Soule Cody
• Twombly John G
• Brigham Michael
• Porth Bruce
• Kalaparthi Vivekanand

Classifications

• H10W20/4441

  the principal metal being a refractory metal · CPC title

• H10W20/023 Primary

  the interconnections being through-semiconductor vias · CPC title

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/0261

  characterised by the filling method or the material of the conductive fill · CPC title

• H10W20/20 Primary

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title