RRAM voltage compensation

Patent metadata

Field	Value
Publication number	US-12380948-B2
Application number	US-202217721985-A
Country	US
Kind code	B2
Filing date	Apr 15, 2022
Priority date	Jul 16, 2018
Publication date	Aug 5, 2025
Grant date	Aug 5, 2025

Abstract

A memory device includes an array of resistive memory cells with a plurality of word lines connected to the array of resistive memory cells. A voltage compensation controller is configured to determine a word line voltage to be applied to a selected word line of the plurality of word lines. A word line driver is configured apply the determined word line voltage to the selected word line.

First claim

What is claimed is:

1. A memory device comprising
an array of memory cells comprising a plurality of word lines;
a voltage compensation controller configured to:
receive a first address corresponding to a first selected word line of the plurality of word lines,
determine, based on the first address, a first segment from a plurality of segments in which the first selected word line is located in, wherein the plurality of word lines are grouped into the plurality of segments each comprising a predetermined number of word lines of the plurality of word lines,
determine, based on a first segment identifier, a first word line voltage comprising a first predetermined word line voltage associated with the first segment in which the first selected word line is located in to be applied to the first selected word line, wherein each segment of the plurality of segments is associated with a predetermined word line voltage, wherein the first segment identifier is appended as additional bits to a first word line address of the first selected word line, the segment identifier identifying the first segment of the first word line according to its location, and wherein the segment identifier, and wherein the first word line voltage is generated by switching one or more switches controlling a resistor ladder of the voltage compensation controller based on the segment identifier,
receive a second address corresponding to a second selected word line of the plurality of word lines, and
determine a second word line voltage to be applied to the second selected word line, wherein the second word line voltage to be applied to the second selected word line is lower than the first word line voltage to be applied to the first selected word line.

2. The memory device of claim 1 , wherein the first selected word line of the plurality of word lines is nearer to an I/O block of the memory device than to the second selected word line of the plurality of word lines.

3. The memory device of claim 1 , wherein the plurality of word lines are segmented into the plurality of segments based a distance of each of the plurality of word lines from the I/O block.

4. The memory device of claim 3 , wherein the plurality of segments comprises the first segment comprising the first selected word line and a second segment comprising the second selected word line, wherein the first segment is assigned the first predetermined word line voltage, and wherein the second segment is assigned a second predetermined word line voltage.

5. The memory device of claim 1 , wherein the voltage compensation controller comprises a location compensation module and a temperature compensation module.

6. The memory device of claim 5 , wherein the location compensation module determines a location compensated first word line voltage to be applied to the first selected word line based on a first distance of the first selected word line from an I/O block of the memory device.

7. The memory device of claim 5 , wherein the temperature compensation module determines a temperature compensated first word line voltage to be applied to the first selected word line based on a first temperature of the first selected word line.

8. The memory device of claim 1 , wherein the array of resistive memory cells includes a first sub array and a second sub array, and wherein the voltage compensation controller is positioned between the first array and the second sub array.

9. A method, comprising:
receiving a first address corresponding to a first selected word line of a plurality of word lines of a memory device;
determining, based on the first address, a first segment from a plurality of segments in which the first selected word line is located in, wherein the plurality of word lines are grouped into the plurality of segments each comprising a predetermined number of word lines of the plurality of word lines;
determining, based on a first segment identifier, a first word line voltage comprising a first predetermined word line voltage associated with the first segment in which the first selected word line is located in, wherein each segment of the plurality of segments is associated with a predetermined word line voltage, wherein the first segment identifier is appended as additional bits to a first word line address of the first selected word line, the segment identifier identifying the first segment of the first word line according to its location, and wherein the first word line voltage is generated by switching one or more switches controlling a resistor ladder of the voltage compensation controller based on the segment identifier;
receiving a second address corresponding to a second selected word line of the plurality of word lines; and
determining a second word line voltage to be applied to the second selected word line, wherein the second word line voltage is lower than the first word line voltage.

10. The method of claim 9 , further comprising:
segmenting the plurality of word lines of the array of resistive memory cells into the plurality of segments based on a location of each of the plurality of word lines from an I/O block; and
associating the predetermined word line voltage of a plurality of predetermined word line voltages to each of the plurality of segments.

11. The method of claim 10 , wherein associating the predetermined word line voltage of the plurality of predetermined word line voltages to each of the plurality of segments comprises:
associating the first predetermined word line voltage to the first segment; and
associating a second predetermined word line voltage to the second segment, wherein the second predetermined word line voltage is lower than the first predetermined word line voltage.

12. The method of claim 9 , further comprising:
determining a temperature of the array of resistive memory cells;
determining a minimum word line voltage at a first temperature;
determining a maximum word line voltage at a second temperature higher than the first temperature;
determining a temperature compensated word line voltage for the first word line voltage that increases in proportion to the temperature of the array of resistive memory cells from the minimum word line voltage at the first temperature to the maximum voltage at the second temperature higher than the first temperature.

13. The method of claim 12 , wherein the temperature compensated word line voltage increases linearly from the minimum word line voltage at the first temperature to the maximum word line voltage at the second temperature.

14. A memory device comprising
an array of memory cells comprising a plurality of word lines;
an Input/Output (I/O) circuit connected to the array of memory cells; and
a voltage compensation controller configured to:
receive a first address corresponding to a first selected word line of the plurality of word lines,
determine, based on the first address, a first segment from a plurality of segments in which the first selected word line is located in, wherein the plurality of word lines are grouped into the plurality of segments each comprising a predetermined number of word lines of the plurality of word lines,
determine, based on a first segment identifier, a first word line voltage comprising a first predetermined word line voltage associated with the first segment in which the first selected word line is located in to be applied to the first selected word line, wherein each segment of the plurality of segments is associated with a predetermined word line voltage, wherein the first segment identifier is appended as additional bits to a first word line address of the first selected word line

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lai Chien-An
• Chou Chung-Cheng
• Chih Yu-Der

Classifications

• G11C13/004

  Reading or sensing circuits or methods · CPC title

• G11C2013/0045

  Read using current through the cell · CPC title

• G11C7/04

  with means for avoiding disturbances due to temperature effects · CPC title

• G11C7/1063

  Control signal output circuits, e.g. status or busy flags, feedback command signals · CPC title

• G11C13/0069

  Writing or programming circuits or methods · CPC title