Pseudo-static random access memory

Patent metadata

Field	Value
Publication number	US-12380933-B2
Application number	US-202217960433-A
Country	US
Kind code	B2
Filing date	Oct 5, 2022
Priority date	Nov 8, 2021
Publication date	Aug 5, 2025
Grant date	Aug 5, 2025

Abstract

A pseudo-static random access memory is provided herein, which may improve the speed of data transmission. After a first delay from a command and a row address being input in a first operation, the pseudo-static random access memory inputs or outputs the data in the memory cells corresponding to the input row address and the input column address, which includes a control unit controlling a delay in the second operation less than the initial delay when a specific condition is satisfied. The second operation is executed after the first operation.

First claim

What is claimed is:

1. A pseudo-static random access memory inputting or outputting data to/from memory cells corresponding to a row address and a column address that are input in a first operation after an initial delay starting from a moment that a command and the row address are input, comprising:
a control unit, controlling a delay in a second operation less than the initial delay when a specific condition is satisfied, wherein the second operation is executed after the first operation.

2. The pseudo-static random access memory as defined in claim 1 ,
wherein the specific condition comprises: inputting a specific command in the first operation, wherein the specific command is configured to make the delay in the second operation less than the initial delay.

3. The pseudo-static random access memory as defined in claim 2 ,
wherein the specific command comprises: a read command or a write command that is configured to not precharge a word line corresponding to the row address that has been input.

4. The pseudo-static random access memory as defined in claim 3 ,
wherein the control unit further comprises:
a precharge signal generation unit, generating a precharge enable signal based on the input command, wherein the precharge enable signal indicates whether to precharge the word line corresponding to the row address that is input;
a precharge control unit, precharging the word line corresponding to the row address that is input when the precharge enable signal indicates for precharging; and
a delay control unit, controlling the delay in the second operation less than the initial delay when the precharge enable signal indicates for not precharging;
wherein the precharge signal generation unit is configured to provide the precharge enable signal indicating not to precharge the word line corresponding to the row address to the precharge control unit and the delay control unit when a register writing command indicating not to precharge is input.

5. The pseudo-static random access memory as defined in claim 2 ,
wherein the specific command comprises a register writing command.

6. The pseudo-static random access memory as defined in claim 5 ,
wherein the control unit further comprises:
a precharge signal generation unit, generating a precharge enable signal based on the input command, wherein the precharge enable signal indicates whether to precharge the word line corresponding to the row address that is input;
a precharge control unit, precharging the word line corresponding to the row address that is input when the precharge enable signal indicates to precharge; and
a delay control unit, controlling the delay in the second operation less than the initial delay when the precharge enable signal indicates not to precharge;
wherein the precharge signal generation unit is configured to provide the precharge enable signal indicating not to precharge the word line corresponding to the row address to the precharge control unit and the delay control unit when a register writing command indicating not to precharge is input.

7. The pseudo-static random access memory as defined in claim 1 , wherein the specific condition comprises inputting an identical row address in the first operation and the second operation.

8. The pseudo-static random access memory as defined in claim 7 , wherein when the specific condition is satisfied, the control unit controls a delay in each successive operation less than the initial delay while the identical row address in each successive operation following the second operation is being input.

9. The pseudo-static random access memory as defined in claim 7 , wherein the control unit further comprises:
a comparator, comparing the row address input in an n-th (n is greater than 1) operation with the row address input in an (n−1)-th operation to output a comparison result; and
a delay control unit, wherein when the comparison result indicates that the row address input in the n-th operation and the row address input in the (n−1)-th operation are identical, a delay in the n-th operation is controlled to be less than the initial delay.

10. The pseudo-static random access memory as defined in claim 1 , wherein the specific condition comprises: an error has been detected in written data input in the first operation.

11. The pseudo-static random access memory as defined in claim 10 , wherein the control unit further comprises:
an error detection unit, detecting whether the written data input in the first operation has an error; and
a delay control unit, controlling a delay in the second operation to be less than the initial delay when it is detected that the written data input in the first operation has an error.

12. The pseudo-static random access memory as defined in claim 1 , wherein the pseudo-static random access memory is one of the following:
(i) a pseudo-static random access memory synchronous with a clock signal to input or output a signal; or
(ii) a pseudo-static random access memory with an address data multiplexing interface.

Assignees

• Winbond Electronics Corp
• Windbond Electronics Corp

Inventors

• Ikeda Hitoshi
• Sato Takahiko

Classifications

• G11C7/1063

  Control signal output circuits, e.g. status or busy flags, feedback command signals · CPC title

• G11C7/1048

  Data bus control circuits, e.g. precharging, presetting, equalising · CPC title

• G11C29/50012

  of timing · CPC title

• G11C2207/2272

  Latency related aspects · CPC title

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title