Driving thin film switchable optical devices

Patent metadata

Field	Value
Publication number	US-12379639-B2
Application number	US-202418605605-A
Country	US
Kind code	B2
Filing date	Mar 14, 2024
Priority date	Mar 16, 2011
Publication date	Aug 5, 2025
Grant date	Aug 5, 2025

Abstract

Controllers and control methods apply a drive voltage to bus bars of a thin film optically switchable device. The applied drive voltage is provided at a level that drives a transition over the entire surface of the optically switchable device but does not damage or degrade the device. This applied voltage produces an effective voltage at all locations on the face of the device that is within a bracketed range. The upper bound of this range is associated with a voltage safely below the level at which the device may experience damage or degradation impacting its performance in the short term or the long term. At the lower boundary of this range is an effective voltage at which the transition between optical states of the device occurs relatively rapidly. The level of voltage applied between the bus bars is significantly greater than the maximum value of the effective voltage within the bracketed range.

First claim

What is claimed is:

1. A controller for controlling an optical state of an electrochromic device, the controller comprising:
circuitry for applying voltage or providing instructions to apply voltage between bus bars on the electrochromic device; and
a processing component configured to cause:
providing a constant current to the electrochromic device during a first time period;
ceasing providing the constant current to the electrochromic device when a first target condition is met;
providing a variable current to the electrochromic device during a second time period after the first target condition is met; and
providing a hold voltage to the electrochromic device when a second target condition is met.

2. The controller of claim 1 , wherein the first target condition relates to one or more regions of the electrochromic device reaching a first target voltage during the first time period.

3. The controller of claim 2 , wherein the first target voltage corresponds to a maximum safe voltage for the electrochromic device.

4. The controller of claim 1 , wherein the first target condition relates to a first target duration during the first time period.

5. The controller of claim 1 , wherein the first target condition relates to a first target charge passed to the electrochromic device during the first time period.

6. The controller of claim 1 , wherein the second target condition relates to a second target charge passed to the electrochromic device during the second time period or during the first and second time periods.

7. The controller of claim 6 , wherein providing the hold voltage to the electrochromic device occurs after the electrochromic device reaches a target optical state.

8. The controller of claim 1 , wherein the second target condition relates to a second target duration during the second time period or during the first and second time periods.

9. The controller of claim 1 , wherein the first target condition relates to one or more regions of the electrochromic device reaching a first target voltage during the first time period, and wherein the second target condition relates to a second target charge passed to the electrochromic device during the second time period or during the first and second time periods.

10. The controller of claim 1 , wherein the electrochromic device transitions from a first optical state to a second optical state over the course of the first and second time periods.

11. The controller of claim 1 , wherein the processing component is configured to cause monitoring the current provided to the electrochromic device, and monitoring the voltage provided to the electrochromic device.

12. The controller of claim 1 , wherein both the constant current and the variable current are provided to the bus bars of the electrochromic device.

13. The controller of claim 1 , wherein a voltage provided to the electrochromic device is controlled during the second time period.

14. The controller of claim 13 , wherein a profile of the current provided to the electrochromic device is in accordance with a profile of the voltage provided to the electrochromic device.

15. The controller of claim 1 , wherein during the first time period, the controlled current provided to the electrochromic device is between I slow and I safe , wherein I slow corresponds to a current level at which the electrochromic device transitions its optical state at an unacceptably slow rate, and I safe corresponds to a current level above which the electrochromic device can become damaged or degraded.

16. The controller of claim 15 , wherein I slow is between about 1 μA/cm 2 and about 30 μA/cm 2 , and wherein I safe is between about 70 μA/cm 2 and about 250 μA/cm 2 .

17. The controller of claim 1 , wherein the constant current is between about 30 μA/cm 2 and about 70 μA/cm 2 .

18. The controller of claim 1 , wherein the processing component is configured to cause applying a voltage ramp to the electrochromic device during the first time period, the voltage ramp resulting in the constant current provided to the electrochromic device.

19. The controller of claim 18 , wherein the processing component is configured to cause adjusting or temporarily pausing the voltage ramp during the first time period to maintain the constant current between I slow and I safe , wherein I slow corresponds to a current level at which the electrochromic device transitions its optical state at an unacceptably slow rate, and I safe corresponds to a current level above which the electrochromic device can become damaged or degraded.

Assignees

• View Inc
• View Operating Corp

Inventors

• Pradhan Anshu A
• Mehtani Disha
• Jack Gordon

Classifications

• G02F2001/1555

  Counter electrode · CPC title

• G02F1/155

  Electrodes · CPC title

• G02F1/15

  based on an electrochromic effect · CPC title

• G02F1/163 Primary

  Operation of electrochromic cells, e.g. electrodeposition cells; Circuit arrangements therefor · CPC title