Semiconductor wafer made of single-crystal silicon and process for the production thereof

Patent metadata

Field	Value
Publication number	US-12378692-B2
Application number	US-202118011949-A
Country	US
Kind code	B2
Filing date	May 28, 2021
Priority date	Jun 25, 2020
Publication date	Aug 5, 2025
Grant date	Aug 5, 2025

Abstract

A semiconductor wafer of single-crystal silicon has an oxygen concentration per new ASTM of not less than 5.0×10 17 atoms/cm 3 and not more than 6.5×10 17 atoms/cm 3 ; a nitrogen concentration per new ASTM of not less than 1.0×10 13 atoms/cm 3 and not more than 1.0×10 14 atoms/cm 3 ;
a front side having a silicon epitaxial layer wherein the semiconductor wafer has BMDs whose mean size is not more than 10 nm determined by transmission electron microscopy and whose mean density adjacent to the epitaxial layer is not less than 1.0×10 11 cm −3 , determined by reactive ion etching after having subjected the wafer covered with the epitaxial layer to a heat treatment at a temperature of 780° C. for a period of 3 h and to a heat treatment at a temperature of 600° C. for a period of 10 h.

First claim

The invention claimed is:

1. A single-crystal silicon semiconductor wafer having an oxygen concentration per new ASTM of not less than 5.0×10 17 atoms/cm 3 and not more than 6.5×10 17 atoms/cm 3 and a nitrogen concentration per new ASTM of not less than 1×10 13 atoms/cm 3 and not more than 1.0×10 14 atoms/cm 3 , wherein a front side of the semiconductor wafer is covered with a silicon epitaxial layer, and wherein the semiconductor wafer comprises BMDs whose mean diagonal size is not more than 10 nm determined by transmission electron microscopy, and whose mean density in a region adjacent to the epitaxial layer is not less than 1.0×10 11 cm −3 , determined by reactive ion etching after having subjected the wafer covered with the epitaxial layer to a two stage heat treatment, a first heat treatment, at a temperature of 780° C. for a period of 3 h, followed by a second heat treatment at a temperature of 600° C. for a period of 10 h,
wherein dislocation loops are present in a region of the semiconductor wafer that is spaced apart from an interface between the epitaxial layer and the front side of the semiconductor wafer by not less than 2 μm and not more than 7 μm and has a depth of at least 35 μm.

2. The wafer of claim 1 , wherein the oxygen concentration is not less than 5.7×10 17 atoms/cm 3 and not more than 6.2×10 17 atoms/cm 3 .

3. The wafer of claim 1 , wherein the semiconductor wafer has a nickel getter efficiency of at least 95%, the nickel getter efficiency being defined as the total intentional contamination of Ni minus the amount of Ni on both wafer surface regions compared to the total intentional contamination of Ni.

4. The wafer of claim 3 , wherein the mean density of BMDs decreases in the region adjacent to the epitaxial layer in a depth direction.

5. The wafer of claim 3 , wherein the oxygen concentration is not less than 5.7×10 17 atoms/cm 3 and not more than 6.2×10 17 atoms/cm 3 .

6. The wafer of claim 1 , wherein the mean density of BMDs decreases in the region adjacent to the epitaxial layer in a depth direction.

7. The wafer of claim 6 , wherein the oxygen concentration is not less than 5.7×10 17 atoms/cm 3 and not more than 6.2×10 17 atoms/cm 3 .

Assignees

• Siltronic Ag

Inventors

• Sattler Andreas
• Vetterhoeffer Juergen

Classifications

• H10P90/12 Primary

  Preparing bulk and homogeneous wafers · CPC title

• H10P36/20

  Intrinsic gettering, i.e. thermally inducing defects by using oxygen present in the silicon body · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/36

  characterised by treatments done before the formation of the materials · CPC title

• H10P14/2905

  Silicon, silicon germanium or germanium · CPC title