Display substrate and display apparatus

Patent metadata

Field	Value
Publication number	US-12376461-B2
Application number	US-202218264041-A
Country	US
Kind code	B2
Filing date	Nov 17, 2022
Priority date	Nov 17, 2022
Publication date	Jul 29, 2025
Grant date	Jul 29, 2025

Abstract

A display substrate is provided. The display substrate includes a display substrate, comprising one or more scan circuits and one or more electrostatic discharge protection circuits in a peripheral area. An electrostatic discharge protection circuit is configured to provide a start signal to a scan unit of a scan circuit. The display substrate comprises a plurality of islands and a plurality of bridges connecting the plurality of islands in the peripheral area; a respective island of the plurality of islands comprises at least one scan unit of the scan circuit; and one or more signal lines connecting the electrostatic discharge protection circuit and the scan unit is at least partially in an individual bridge connecting the electrostatic discharge protection circuit and the scan unit.

First claim

What is claimed is:

1. A display substrate, comprising one or more scan circuits and one or more electrostatic discharge protection circuits in a peripheral area;
wherein an electrostatic discharge protection circuit is configured to provide a start signal to a scan unit of a scan circuit;
wherein the display substrate comprises a plurality of islands and a plurality of bridges connecting the plurality of islands in the peripheral area;
a respective island of the plurality of islands comprises at least one scan unit of the scan circuit; and
one or more signal lines connecting the electrostatic discharge protection circuit and the scan unit is at least partially in an individual bridge connecting the electrostatic discharge protection circuit and the scan unit;
wherein the electrostatic discharge protection circuit comprises:
a first reference voltage terminal configured to receive a first reference voltage from the scan circuit;
a second reference voltage terminal configured to receive a second reference voltage from the scan circuit;
a node configured to output the start signal; and
a connecting line connecting the node to an input terminal of the scan unit.

2. The display substrate of claim 1 , wherein the connecting line at least partially extends through the individual bridge.

3. The display substrate of claim 1 , wherein the first reference voltage terminal, the second reference voltage terminal, and the connecting line are in a first signal line layer; and
the node is in a semiconductor material layer different from the first signal line layer.

4. The display substrate of claim 1 , further comprising:
a start signal lead line electrically connects a start signal terminal to a start signal line in the scan circuit;
a first lead line electrically connecting the first reference voltage terminal to a first reference signal line in the scan circuit; and
a second lead line electrically connecting the second reference voltage terminal to a second reference signal line in the scan circuit.

5. The display substrate of claim 4 , wherein the start signal lead line, the first lead line, and the second lead line are at least partially in a second signal line layer.

6. The display substrate of claim 4 , wherein the start signal lead line, the first lead line, and the second lead line at least partially extend through the individual bridge.

7. The display substrate of claim 1 , wherein the electrostatic discharge protection circuit is in a respective first island of the plurality of islands;
the scan unit is in a respective second island of the plurality of islands; and
the respective first island and the respective second island are adjacent to each other.

8. The display substrate of claim 7 , wherein the peripheral area includes a first sub-area on a first side of a display area, a second sub-area on a second side of the display area, a third sub-area on a third side of the display area, and a fourth sub-area on a fourth side of the display area;
the electrostatic discharge protection circuit is in the third sub-area and/or the fourth sub-area;
the display substrate is at least partially stretchable in the first sub-area, the second sub-area, the third sub-area, and the fourth sub-area.

9. The display substrate of claim 1 , wherein the one or more scan circuits comprise a first scan circuit and a second scan circuit; and
the one or more electrostatic discharge protection circuits comprise a first electrostatic discharge protection circuit and a second electrostatic discharge protection circuit.

10. The display substrate of claim 9 , in the peripheral area, comprises a respective first island, a respective second island, a respective third island, and a respective fourth island arranged in rows and columns;
the respective first island and the respective second island are arranged in a first column;
the respective third island and the respective fourth island are arranged in a second column;
the respective first island and the respective third island are arranged in a first row; and
the respective second island and the respective fourth island are arranged in a second row.

11. The display substrate of claim 10 , wherein the first electrostatic discharge protection circuit and the second electrostatic discharge protection circuit are at least partially in the respective first island;
a 1 st scan unit of the first scan circuit is at least partially in the respective second island;
a 1 st scan unit of the second scan circuit is at least partially in the respective third island; and
a 2 nd scan unit of the second scan circuit is at least partially in the respective fourth island.

12. The display substrate of claim 11 , wherein the second scan circuit is a control signal generating circuit configured to generate gate scanning signals and reset control signals for subpixels in a display substrate; and
the 1 st scan unit of the second scan circuit is configured to provide a reset control signal to a first row of subpixels in a display area.

13. The display substrate of claim 1 , wherein the first reference voltage is a high power supply voltage; and
the second reference voltage is a low power supply voltage.

14. A display apparatus, comprising the display substrate of claim 1 , and one or more integrated circuits connected to the display substrate.

15. A display substrate, comprising one or more scan circuits and one or more electrostatic discharge protection circuits in a peripheral area;
wherein an electrostatic discharge protection circuit is configured to provide a start signal to a scan unit of a scan circuit;
wherein the display substrate comprises a plurality of islands and a plurality of bridges connecting the plurality of islands in the peripheral area;
a respective island of the plurality of islands comprises at least one scan unit of the scan circuit; and
one or more signal lines connecting the electrostatic discharge protection circuit and the scan unit is at least partially in an individual bridge connecting the electrostatic discharge protection circuit and the scan unit;
wherein the electrostatic discharge protection circuit comprises:
a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
a start signal terminal;
a first reference voltage terminal configured to receive a first reference voltage from the scan circuit;
a second reference voltage terminal configured to receive a second reference voltage from the scan circuit; and
a node electrically connected between the second transistor and the third transistor and electrically connected to the start signal terminal.

16. The display substrate of claim 15 , wherein a first electrode and a gate electrode of the first transistor are electrically connected to the first reference voltage terminal;
a second electrode of the first transistor is electrically connected to a first electrode and a gate electrode of the third transistor;
a second electrode of the third transistor is electrically connected to the node;
a first electrode of the second transistor is electrically connected to the node;
a gate electrode of the second transistor is electrically connected to the start signal terminal;
a second electrode of the second transistor is electrically connected to a first electrode and a gate electrode of the fourth transistor; and
a second electrode of the fourth transistor is electrically connected to the second reference voltage terminal.

17. The display substrate of claim 15 , wherein, when a voltage of the start signal terminal i

Assignees

• Boe Technology Group Co Ltd

Inventors

• Zhang Hao
• Wang Pinfan
• Liu Fang

Classifications

• G09G2330/04

  Display protection · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title