Process for fabricating a semiconductor diode via wet and dry etches

Patent metadata

Field	Value
Publication number	US-12376423-B2
Application number	US-202217931718-A
Country	US
Kind code	B2
Filing date	Sep 13, 2022
Priority date	Sep 14, 2021
Publication date	Jul 29, 2025
Grant date	Jul 29, 2025

Abstract

The invention relates to a process for fabricating a semiconductor diode (1) via transfer of a semiconductor stack (20) then local etching to form a semiconductor pad (30), the production of the semiconductor pad (30) comprising a plurality of sequences comprising a dry etch that leaves a residual segment (23.1; 22.1), formation of a hard-mask spacer (42.1; 43.1), then a wet etch of the residual segment (23.1; 22.1).

First claim

The invention claimed is:

1. A process for fabricating a semiconductor diode, comprising the following steps:
transfer of a semiconductor stack to a carrier substrate, comprising, starting from the carrier substrate: a lower layer doped with a first conductivity type dopant; an active layer comprising at least one quantum well; and an upper layer doped with a second conductivity type dopant opposite the first conductivity type dopant; and
production, by local etching of the semiconductor stack, of a semiconductor pad comprising: a doped lower segment; an active segment having a lateral dimension smaller than that of the doped lower segment; and a doped upper segment having a lateral dimension smaller than that of the active segment, said production of the semiconductor pad comprising the following steps:
depositing a first hard mask on the upper layer;
forming the doped upper segment by dry etching the upper layer, with the dry etching of the upper layer stopped on the active layer, a lateral segment of the upper layer not entirely etched and forming a first residual segment resting on the active layer;
forming a first spacer by depositing and structuring a second hard mask, the first spacer encapsulates the doped upper segment and leaves free an upper surface of the active layer and one portion of the first residual segment;
wet etching the first residual segment selectively with respect to the active layer, freeing a surface of the active layer not covered by the first spacer;
forming the active segment by dry etching the active layer, with the dry etching of the active layer stopped on the lower layer, a lateral segment of the active layer being not entirely etched and forming a second residual segment resting on the lower layer;
forming a second spacer by depositing and structuring a third hard mask, the second spacer laterally encircles the first spacer and the active segment, and leaves free an upper surface of the lower layer and one portion of the second residual segment; and
wet etching the second residual segment selectively with respect to the lower layer, freeing a surface of the lower layer not covered by the second spacer.

2. The fabricating process as claimed in claim 1 , wherein the second hard mask and the third hard mask have, before they are structured, a thickness smaller than that of the semiconductor stack before the step of dry etching the upper layer.

3. The fabricating process as claimed in claim 1 , comprising a step of locally etching the portion of the lower layer not covered by the second spacer to form the doped lower segment.

4. The fabricating process as claimed in claim 1 , wherein the first, second, and third hard masks comprise silicon nitride.

5. The fabricating process as claimed in claim 1 , wherein the second and third hard masks are made of a silicon nitride, or are formed of a bilayer comprising a silicon-nitride first sub-layer and a second sub-layer made of an oxide or of a silane.

6. The fabricating process as claimed in claim 1 , wherein the semiconductor pad comprises a III-V compound, a II-VI compound, or a IV compound or element.

7. The fabricating process as claimed in claim 1 , wherein the semiconductor pad comprises a III-V compound, and the carrier substrate is a silicon-on-insulator substrate.

8. The fabricating process as claimed in claim 1 , wherein the semiconductor diode is a hybrid laser diode, and the semiconductor pad forms a waveguide optically coupled to an integrated waveguide located in the carrier substrate.

Assignees

• Commissariat Energie Atomique
• Commissariat A Lenergie Atomique Et Aux Energies

Inventors

• Szelag Bertrand
• Adelmini Laetitia

Classifications

• H01S5/026

  Monolithically integrated components, e.g. waveguides, monitoring photo-detectors, drivers (stabilisation of output H01S5/06) · CPC title

• H01S5/1032

  Coupling to elements comprising an optical axis that is not aligned with the optical axis of the active region · CPC title

• H01S5/021

  Silicon based substrates · CPC title

• H01S2301/176

  Specific passivation layers on surfaces other than the emission facet · CPC title

• H01S5/02

  Structural details or components not essential to laser action · CPC title