Pixel circuit with specific transistor layout and display substrate

Patent metadata

Field	Value
Publication number	US-12376376-B2
Application number	US-202117772536-A
Country	US
Kind code	B2
Filing date	Apr 28, 2021
Priority date	Apr 28, 2021
Publication date	Jul 29, 2025
Grant date	Jul 29, 2025

Abstract

A display substrate and a display panel are provided. The display substrate includes a base substrate; a display region, on the base substrate and including a plurality of sub-pixels arranged in an array; each of the plurality of sub-pixels includes a light-emitting element and a pixel circuit that drives the light-emitting element to emit light, and the pixel circuit includes a driving sub-circuit, a data writing sub-circuit, a threshold compensation sub-circuit, and a reset sub-circuit; the reset sub-circuit includes a first reset transistor and a second reset transistor, the threshold compensation sub-circuit includes a threshold compensation transistor and a storage capacitor, an orthographic projection of the second reset transistor on the base substrate is between an orthographic projection of the first reset transistor on the base substrate and an orthographic projection of the threshold compensation transistor on the base substrate.

First claim

What is claimed is:

1. A display substrate, comprising:
a base substrate; and
a display region, on the base substrate and comprising a plurality of sub-pixels arranged in an array,
wherein each of the plurality of sub-pixels comprises a light-emitting element and a pixel circuit that drives the light-emitting element to emit light, and the pixel circuit comprises a driving sub-circuit, a data writing sub-circuit, a threshold compensation sub-circuit, and a reset sub-circuit;
the driving sub-circuit comprises a control terminal, a first terminal, and a second terminal, and is configured to control a driving current flowing through the light-emitting element;
the data writing sub-circuit is connected to the first terminal of the driving sub-circuit, a data line, and a scan signal line, and is configured to write a data signal provided by the data line to the first terminal of the driving sub-circuit in response to a gate scan signal provided by the scan signal line;
the threshold compensation sub-circuit is connected to the control terminal and the second terminal of the driving sub-circuit, a first voltage line, and a first reset control signal terminal, and is configured to compensate the driving sub-circuit in response to a first reset control signal received by the first reset control signal terminal and the data signal written; and
the reset sub-circuit is connected to the second terminal of the driving sub-circuit, a first light-emitting control signal line, an initial signal line, and a second reset control signal terminal, and is configured to apply an initial voltage provided by the initial signal line to the second terminal of the driving sub-circuit in response to a first light-emitting control signal provided by the first light-emitting control signal line and a second reset control signal received by the second reset control signal terminal,
wherein the reset sub-circuit comprises a first reset transistor and a second reset transistor, the threshold compensation sub-circuit comprises a threshold compensation transistor and a storage capacitor, an orthographic projection of the second reset transistor on the base substrate is between an orthographic projection of the first reset transistor on the base substrate and an orthographic projection of the threshold compensation transistor on the base substrate, and an orthographic projection of the storage capacitor on the base substrate is between the orthographic projection of the second reset transistor on the base substrate and the orthographic projection of the threshold compensation transistor on the base substrate;
wherein gate electrodes of the first reset transistor are connected to the second reset control signal terminal to receive the second reset control signal, and a gate electrode of the second reset transistor is connected to the first light-emitting control signal line to receive the first light-emitting control signal.

2. The display substrate according to claim 1 , wherein the pixel circuit further comprises a first light-emitting control sub-circuit and a second light-emitting control sub-circuit;
the first light-emitting control sub-circuit is connected to the second terminal of the driving sub-circuit, a first terminal of the light-emitting element, and the first light-emitting control signal line, and is configured to apply the driving current to the light-emitting element in response to the first light-emitting control signal provided by the first light-emitting control signal line; and
the second light-emitting control sub-circuit is connected to the first voltage line, the first terminal of the driving sub-circuit, and the second light-emitting control signal line, and is configured to apply a first voltage provided by the first voltage line to the first terminal of the driving sub-circuit in response to the second light-emitting control signal provided by the second light-emitting control signal line,
wherein the first light-emitting control signal line and the second light-emitting control signal line extend along a first direction, an orthographic projection of the first light-emitting control signal line on the base substrate is between an orthographic projection of the second light-emitting control signal line on the base substrate and the orthographic projection of the storage capacitor on the base substrate.

3. The display substrate according to claim 2 , wherein the orthographic projection of the second light-emitting control signal line on the base substrate is between the orthographic projection of the first light-emitting control signal line on the base substrate and the orthographic projection of the storage capacitor on the base substrate.

4. The display substrate according to claim 2 , wherein the first light-emitting control sub-circuit comprises a first light-emitting control transistor;
an active layer of the threshold compensation transistor, an active layer of the first light-emitting control transistor, and an active layer of the second reset transistor are integrally formed; and
a gate electrode of the first light-emitting control transistor and the gate electrode of the second reset transistor are parallel in the first direction.

5. The display substrate according to claim 4 , wherein the gate electrode of the first light-emitting control transistor and the gate electrode of the second reset transistor are integrally formed with the second light-emitting control signal line.

6. The display substrate according to claim 4 , further comprising a first connection line extending along the first direction,
wherein the first connection line is connected to second light-emitting control signal lines respectively corresponding to adjacent sub-pixels through holes penetrating an insulation layer.

7. The display substrate according to claim 1 , wherein sub-pixels in an x-th column and sub-pixels in an (x+1)-th column are mirror-symmetrical; and
an active layer of a first reset transistor of each sub-pixel in the x-th column and an active layer of a first reset transistor of each sub-pixel in the (x+1)-th column are both U-shaped structures, and the U-shaped structures share one side,
wherein x is an odd or even number greater than 0.

8. The display substrate according to claim 6 , wherein the first reset transistor comprises a first gate electrode and a second gate electrode, an active layer of the first reset transistor comprises a first channel region corresponding to the first gate electrode, a second channel region corresponding to the second gate electrode, and a first intermediate region between the first channel region and the second channel region, and the first channel region and the second channel region are connected through the first intermediate region; and
the threshold compensation transistor comprises a third gate electrode and a fourth gate electrode, the active layer of the threshold compensation transistor comprises a third channel region corresponding to the third gate electrode, a fourth channel region corresponding to the fourth gate electrode, and a second intermediate region between the third channel region and the fourth channel region, and the third channel region and the fourth channel region are connected through the second intermediate region.

9. The display substrate according to claim 8 , wherein the initial signal line comprises a first initial sub-signal line and a second initial sub-signal line extending along the first direction;
an orthographic projection of the first intermediate region on the base substrate and an orthographic projection of the second initial sub-signal line on the base substrate at least partially overlap; and
an orthographic projection of the second intermediate region on the base

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Han Linhong
• Wang Qiwei
• Huang Yao
• Zeng Chao
• Huang Weiyun

Classifications

• G09G2310/061

  for resetting or blanking · CPC title

• G09G2310/0251

  Precharge or discharge of pixel before applying new pixel voltage · CPC title

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

• G09G3/3648

  using an active matrix (G09G3/367 - G09G3/3696 take precedence) · CPC title

• G09G3/3233

  with pixel circuitry controlling the current through the light-emitting element · CPC title