Dynamic load balancing for multi-core computing environments

Patent metadata

Field	Value
Publication number	US-12375408-B2
Application number	US-202418621516-A
Country	US
Kind code	B2
Filing date	Mar 29, 2024
Priority date	Sep 11, 2019
Publication date	Jul 29, 2025
Grant date	Jul 29, 2025

Abstract

Methods, apparatus, systems, and articles of manufacture are disclosed for dynamic load balancing for multi-core computing environments. An example apparatus includes a first and a plurality of second cores of a processor, and circuitry in a die of the processor separate from the first and the second cores, the circuitry to enqueue identifiers in one or more queues in the circuitry associated with respective ones of data packets of a packet flow, allocate one or more of the second cores to dequeue first ones of the identifiers in response to a throughput parameter of the first core not satisfying a throughput threshold to cause the one or more of the second cores to execute one or more operations on first ones of the data packets, and provide the first ones to one or more data consumers to distribute the first data packets.

First claim

What is claimed is:

1. At least one non-transitory computer readable medium comprising instructions to cause at least one programmable circuit in a semiconductor die to at least:
identify first packets that belong to an elephant packet flow;
queue entries associated with the first packets among different queues of a plurality of queues to distribute the first packets to different cores of a plurality of processor cores in the semiconductor die, the at least one programmable circuit separate from the plurality of processor cores, the plurality of queues respectively associated with the plurality of processor cores; and
queue entries associated with second packets different from the first packets in the queues such that packets of the second packets belonging to a same flow are queued to a same queue of the queues.

2. The at least one non-transitory computer readable medium of claim 1 , wherein the different cores are to process the first packets to produce processed first packets, and the instructions are to cause one or more of the at least one programmable circuit to re-order the processed first packets to produce a processed elephant packet flow.

3. The at least one non-transitory computer readable medium of claim 2 , wherein the first packets are from a first network interface, and the instructions are to cause one or more of the at least one programmable circuit to provide the processed elephant packet flow to a second network interface.

4. The at least one non-transitory computer readable medium of claim 1 , wherein the instructions are to cause one or more of the at least one programmable circuit to identify an input packet flow as the elephant packet flow based on a duration of the input packet flow.

5. The at least one non-transitory computer readable medium of claim 1 , wherein the instructions are to cause one or more of the at least one programmable circuit to identify an input packet flow as the elephant packet flow based on a bandwidth associated with the input packet flow.

6. The at least one non-transitory computer readable medium of claim 1 , wherein the entries associated with the first packets include pointers to the first packets.

7. A semiconductor die comprising:
a plurality of processor cores; and
circuitry in the semiconductor die, the circuitry separate from the plurality of processor cores, the circuitry to:
identify first packets that belong to an elephant packet flow;
queue entries associated with the first packets among different queues of a plurality of queues to distribute the first packets to different cores of the plurality of processor cores, the plurality of queues respectively associated with the plurality of processor cores; and
queue entries associated with second packets different from the first packets in the queues such that packets of the second packets belonging to a same flow are queued to a same queue.

8. The semiconductor die of claim 7 , wherein the different cores are to process the first packets to produce processed first packets, and the circuitry is to cause the processed first packets to be re-ordered to produce a processed elephant packet flow.

9. The semiconductor die of claim 8 , wherein the first packets are from a first network interface, and the circuitry is to cause the processed elephant packet flow to be provided to a second network interface.

10. The semiconductor die of claim 7 , wherein the circuitry is to identify an input packet flow as the elephant packet flow based on a duration of the input packet flow.

11. The semiconductor die of claim 7 , wherein the circuitry is to identify an input packet flow as the elephant packet flow based on a bandwidth associated with the input packet flow.

12. The semiconductor die of claim 7 , wherein the entries associated with the first packets include pointers to the first packets.

13. The semiconductor die of claim 7 , wherein the different cores are to perform cryptographic operations on the first packets.

14. The semiconductor die of claim 7 , wherein the different cores are to perform firewall operations on the first packets.

15. A method comprising:
identifying first packets that belong to an elephant packet flow;
queuing, with circuitry in a semiconductor die, entries associated with the first packets among different queues of a plurality of queues to distribute the first packets to different cores of a plurality of processor cores in the semiconductor die, the circuitry separate from the plurality of processor cores, the plurality of queues respectively associated with the plurality of processor cores; and
queuing, with the circuitry, entries associated with second packets different from the first packets in the queues such that packets of the second packets belonging to a same flow are queued to a same queue of the queues.

16. The method of claim 15 , wherein the different cores are to process the first packets to produce processed first packets, and including re-ordering the processed first packets to produce a processed elephant packet flow.

17. The method of claim 16 , wherein the first packets are from a first network interface, and including providing the processed elephant packet flow to a second network interface.

18. The method of claim 15 , further including identifying an input packet flow as the elephant packet flow based on a duration of the input packet flow.

19. The method of claim 15 , including identifying an input packet flow as the elephant packet flow based on a bandwidth associated with the input packet flow.

20. The method of claim 15 , wherein the entries associated with the first packets include pointers to the first packets.

Assignees

• Intel Corp

Inventors

• Palermo Stephen
• Chaddick Bradley
• Eads Gage
• Ganguli Mrittika
• Khade Abhishek
• Layek Abhirupa
• Maini Sarita
• Mcdonnell Niall
• Shah Rahul
• Shah Shrikant
• Burroughs William
• Sonnier David

Classifications

• H04L47/6275

  based on priority · CPC title

• H04L47/6255

  queue load conditions, e.g. longest queue first · CPC title

• H04L47/624

  Altering the ordering of packets in an individual queue · CPC title

• H04L47/62

  characterised by scheduling criteria · CPC title

• H04L47/125 Primary

  by balancing the load, e.g. traffic engineering · CPC title