Gate driver device having a driver circuit for supplying a backgate drive signal

Patent metadata

Field	Value
Publication number	US-12375081-B2
Application number	US-202418439174-A
Country	US
Kind code	B2
Filing date	Feb 12, 2024
Priority date	Aug 3, 2021
Publication date	Jul 29, 2025
Grant date	Jul 29, 2025

Abstract

A gate driver device includes a first field effect transistor and a first driver circuit. The first field effect transistor includes a first gate electrode and a first backgate structure. The first driver circuit supplies a first backgate drive signal to the first backgate structure.

First claim

What is claimed is:

1. A gate driver device, comprising:
a first field effect transistor comprising a first gate electrode and a first backgate structure, wherein the first backgate structure is a doped semiconductor region separated from active doped regions of the first field effect transistor by a dielectric structure, wherein the active doped regions include a source region of a first conductivity type, a body region of a second conductivity type adjoining the source region, a drain region of the first conductivity type, and a drift region of the first conductivity type laterally separating the body region and the drain region; and
a first driver circuit configured to supply a first backgate drive signal to the first backgate structure.

2. The gate driver device of claim 1 , wherein the first driver circuit is further configured to supply a first gate signal to the first gate electrode.

3. The gate driver device of claim 1 , further comprising:
a first gate signal driver circuit configured to supply a first gate signal to the first gate electrode,
wherein level changes of the first backgate drive signal and the first gate signal are in fixed temporal relation to each other.

4. The gate driver device of claim 3 , wherein the first driver circuit and the first gate driver circuit are configured to receive a common input signal and to generate level changes of the first gate signal and the first backgate drive signal in fixed time relation to level changes of the common input signal.

5. The gate driver device of claim 1 , further comprising:
a second field effect transistor comprising a second gate electrode and a second backgate structure, wherein source-drain paths of the first field effect transistor and the second field effect transistor are electrically connected in series between a positive supply voltage and a supply voltage reference; and
a second driver circuit configured to supply a second backgate drive signal to the second backgate structure.

6. The gate driver device of claim 5 , further comprising:
a second gate signal driver circuit configured to supply a second gate signal to the second gate electrode,
wherein level changes of the second backgate drive signal and the second gate signal are in fixed temporal relation to each other.

7. The gate driver circuit of claim 5 , wherein the first field effect transistor and the second field effect transistor have complementary channel types.

8. The gate driver circuit of claim 1 , wherein the first backgate structure comprises a first well formed in a semiconductor substrate, wherein a conductivity type of the first well is opposite to a conductivity type of a bulk portion of the semiconductor substrate, wherein doped regions of the first field effect transistor are formed in a first semiconductor layer, wherein a dielectric layer is formed between the semiconductor substrate and the first semiconductor layer, and wherein the first driver circuit is configured to supply the first backgate drive signal to the first well.

9. A gate driver circuit, comprising:
a semiconductor substrate that comprises a bulk portion and a first well, wherein a conductivity type of the first well is opposite to a conductivity type of the bulk portion;
a first semiconductor layer comprising doped regions of a first field effect transistor, wherein the doped regions include a source region of a first conductivity type, a body region of a second conductivity type adjoining the source region, a drain region of the first conductivity type, and a drift region of the first conductivity type laterally separating the body region and the drain region;
a dielectric layer between the semiconductor substrate and the first semiconductor layer, wherein the first well and at least a portion of the first semiconductor layer are directly opposite each other; and
a first driver circuit configured to supply a first backgate drive signal to the first well.

10. The gate driver circuit of claim 9 , wherein the first well and at least a portion of the drift region are directly opposite each other.

11. The gate driver circuit of claim 9 , further comprising:
a second well formed in the semiconductor substrate, wherein a conductivity type of the second well is opposite to a conductivity type of the bulk portion; and
a second semiconductor layer comprising doped regions of a second field effect transistor,
wherein the dielectric layer is between the semiconductor substrate and the second semiconductor layer,
wherein the second well and at least a portion of the second semiconductor layer are directly opposite each other.

12. The gate driver circuit of claim 11 , further comprising:
a second driver circuit, wherein an output of the second driver circuit is electrically connected with the second well.

13. The gate driver circuit of claim 11 , wherein the second semiconductor layer comprises a drift region of the second field effect transistor, and wherein the second well and at least a portion of the drift region of the second field effect transistor are directly opposite each other.

14. The gate driver circuit of claim 11 , wherein the first field effect transistor and the second field effect transistor have complementary channel types.

15. The gate driver device of claim 11 , wherein the first field effect transistor comprises a first gate electrode and a first gate dielectric separating the first gate electrode and the first semiconductor layer, and wherein a breakdown strength of the dielectric layer is at least twice as high as a breakdown strength of the first gate dielectric.

16. The gate driver circuit of claim 1 , wherein the doped semiconductor region overlaps with a portion of the drift region oriented to the drain region but does not overlap at all with the body region.

17. The gate driver circuit of claim 1 , wherein the doped semiconductor region overlaps with the entire drift region and with the entire body region.

18. The gate driver circuit of claim 1 , wherein the doped semiconductor region has the second conductivity type.

19. The gate driver circuit of claim 11 , wherein the doped regions of the second field effect transistor include a source region of the second conductivity type, a body region of the first conductivity type adjoining the source region, a drain region of the second conductivity type, and a drift region of the second conductivity type laterally separating the body region and the drain region, and wherein the first well and the second well both have the second conductivity type.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Priefert Dirk
• Albertini Matteo
• Boguszewicz Remigiusz Viktor

Classifications

• H10W10/011

  of isolation regions comprising dielectric materials · CPC title

• H10W10/10

  Isolation regions comprising dielectric materials · CPC title

• H03K2217/0018

  Special modifications or use of the back gate voltage of a FET · CPC title

• H03K17/063

  in field-effect transistor switches · CPC title

• H10D30/6744

  Monocrystalline silicon · CPC title