DC-DC converter circuit, corresponding method of operation and method of trimming a DC-DC converter circuit

Patent metadata

Field	Value
Publication number	US-12374993-B2
Application number	US-202318214646-A
Country	US
Kind code	B2
Filing date	Jun 27, 2023
Priority date	Jul 4, 2022
Publication date	Jul 29, 2025
Grant date	Jul 29, 2025

Abstract

A DC-DC boost converter includes an input receiving an input voltage and an output producing an output voltage. A switching stage is formed by a low-side transistor arranged between a switching node and a ground node, and a high-side transistor arranged between the switching node and the output. The high-side transistor includes a body diode having an anode coupled to the switching node and a cathode coupled to the output. The converter is controlled in an asynchronous operation mode where the low-side transistor is driven alternately to a conductive state and a non-conductive state, and the high-side transistor is driven steadily to a non-conductive state. A variable load circuit is selectively coupled between the two output terminals when the converter is in the asynchronous operation mode in order to sink a load current having a value that is a function of a value of the input voltage.

First claim

The invention claimed is:

1. A DC-DC boost converter circuit, comprising:
first and second input terminals configured to receive an input voltage therebetween;
first and second output terminals configured to produce an output voltage therebetween;
a switching stage comprising a low-side switching transistor arranged between a switching node and a ground node, and a high-side switching transistor arranged between said switching node and said first output terminal, wherein said ground node is coupled to said second input terminal and to said second output terminal, and wherein said high-side switching transistor includes a body diode having an anode terminal coupled to said switching node and a cathode terminal coupled to said first output terminal;
wherein said switching stage is configured for operation in an asynchronous operation mode where said low-side switching transistor is alternately driven to a conductive state and a non-conductive state, and said high-side switching transistor is steadily in a non-conductive state; and
a variable load circuit selectively coupled between said first output terminal and said second output terminal when said switching stage is in said asynchronous operation mode to sink a load current from said first output terminal, and wherein said variable load circuit is configured to sink said load current having a value that is a function of a value of said input voltage.

2. The DC-DC boost converter circuit of claim 1 , wherein said variable load circuit is configured to sink said load current where the value of said load current is linearly dependent on the value of said input voltage.

3. The DC-DC boost converter circuit of claim 1 , wherein said variable load circuit comprises:
a voltage input configured to receive a voltage indicative of said input voltage; and
a current generator circuit configured to generate the load current that is sunk from said first output terminal in response to the voltage received at the voltage input.

4. The DC-DC boost converter circuit of claim 3 , wherein said load current is adjusted as a function of a stored slope trimming value.

5. The DC-DC boost converter circuit of claim 4 , wherein said variable load circuit includes a trimmable resistance for said current generator circuit, and the trimmable resistance is adjusted in response to the stored slope trimming value.

6. The DC-DC boost converter circuit of claim 3 , wherein said load current is adjusted as a function of a stored offset trimming value.

7. The DC-DC boost converter circuit of claim 6 , wherein said variable load circuit includes a trimmable current mirror for said current generator circuit, and a mirroring ratio of said trimmable current mirror is adjusted in response to the stored offset trimming value.

8. The DC-DC boost converter circuit of claim 1 , wherein said variable load circuit comprises:
a differential input pair comprising a first input transistor and a second input transistor, wherein said first input transistor has a control terminal configured to receive a reference voltage, and wherein said second input transistor has a control terminal configured to receive a voltage indicative of said input voltage and is configured to sink a transistor current from a current adder node; and
a current mirror circuit arrangement coupled to said second input transistor at said current adder node and configured to mirror and re-scale a current sunk by said current adder node to produce said load current;
wherein said load current sunk by said variable load circuit is produced as a function of said transistor current sunk by said second input transistor from said current adder node.

9. The DC-DC boost converter circuit of claim 8 , wherein said variable load circuit comprises a voltage divider circuit configured to receive said input voltage and produce, at an intermediate node thereof, said voltage indicative of said input voltage.

10. The DC-DC boost converter circuit of claim 8 , wherein said variable load circuit comprises:
a first trimmable resistor coupled between said first input transistor and a current biasing node, and a second trimmable resistor coupled between said second input transistor and said current biasing node;
a current source coupled between said current biasing node and said ground node and configured to sink a biasing current from said current biasing node;
a further current source coupled between a further current biasing node and said ground node and configured to sink a further biasing current from said further current biasing node; and
a further trimmable current mirror circuit arrangement configured to mirror and re-scale said further biasing current to inject an offset current into said current adder node.

11. The DC-DC boost converter circuit of claim 10 , wherein resistance values of said first trimmable resistor and said second trimmable resistor are trimmable as a function of a stored slope trimming value.

12. The DC-DC boost converter circuit of claim 10 , wherein a mirroring ratio of said further trimmable current mirror circuit arrangement is trimmable as a function of a stored offset trimming value.

13. The DC-DC boost converter circuit of claim 8 , wherein said first input transistor and said second input transistor are trimmable transistors and are directly coupled to a current biasing node; and wherein said variable load circuit comprises a trimmable current source coupled between said current biasing node and said ground node and configured to sink a variable biasing current from said current biasing node.

14. The DC-DC boost converter circuit of claim 13 , wherein a transconductance value of said differential input pair is trimmable as a function of a stored slope trimming value.

15. The DC-DC boost converter circuit of claim 13 , wherein a value of said variable biasing current is trimmable as a function of a stored offset trimming value.

16. A method of operating a DC-DC boost converter circuit, comprising:
receiving an input voltage between first and second input terminals;
producing an output voltage between first and second output terminals;
controlling operation of a switching stage in an asynchronous operation mode by driving a low-side switching transistor alternately to a conductive state and a non-conductive state and driving a high-side switching transistor steadily to a non-conductive state;
coupling a variable load circuit between said first and second output terminals when said switching stage is controlled in said asynchronous operation mode; and
sinking, via a variable load circuit, a load current having a value that is a function of a value of said input voltage.

17. The method of claim 16 , wherein sinking comprises controlling said variable load circuit to sink said load current where the value is linearly dependent on said input voltage.

18. The method of claim 16 , wherein sinking comprises:
sensing a difference between a reference voltage and a voltage indicative of said input voltage to generate a transistor current that is sunk from a current adder node;
mirroring and re-scaling the current sunk by said current adder node to produce said load current;
wherein said load current is produced as a function of said transistor current sunk.

19. A method of trimming a DC-DC boost converter circuit, comprising:
i) operating the converter circuit in an asynchronous operation mode for a selected value of an input voltage with no external load coupled to an output node;
ii) increasing a current output by the converter circuit until

Assignees

• St Microelectronics Srl

Inventors

• Rosa Tommaso
• Bertolini Alessandro
• Ramorini Stefano
• Cattani Alberto

Classifications

• G05F3/247

  producing a voltage or current as a predetermined function of the supply voltage · CPC title

• H02M1/0032

  Control circuits allowing low power mode operation, e.g. in standby mode · CPC title

• H02M1/0045

  Converters combining the concepts of switch-mode regulation and linear regulation, e.g. linear pre-regulator to switching converter, linear and switching converter in parallel, same converter or same transistor operating either in linear or switching mode · CPC title

• H02M1/0009

  Devices or circuits for detecting current in a converter · CPC title

• H02M1/0003

  Details of control, feedback or regulation circuits · CPC title