Semiconductor device, liquid discharge head, and liquid discharge apparatus

Patent metadata

Field	Value
Publication number	US-12374414-B2
Application number	US-202217687482-A
Country	US
Kind code	B2
Filing date	Mar 4, 2022
Priority date	Mar 11, 2021
Publication date	Jul 29, 2025
Grant date	Jul 29, 2025

Abstract

A device, comprising a plurality of units arrayed in a predetermined direction, a first terminal configured to supply a voltage to the plurality of units, and a second terminal configured to supply a voltage to the plurality of units, wherein the plurality of units include a first unit including a memory element arranged between the first terminal and the second terminal, and a first transistor configured to perform write to the memory element, and a second unit including a second transistor arranged between the first terminal and the second terminal in correspondence with the first transistor of the first unit.

First claim

What is claimed is:

1. A device comprising:
a plurality of units arrayed in a predetermined direction;
a first terminal configured to supply a voltage to the plurality of units; and
a second terminal configured to supply a voltage to the plurality of units,
wherein the plurality of units include:
a first unit including a memory element arranged between the first terminal and the second terminal, and a first transistor configured to perform write to the memory element, wherein the first transistor can be controlled to change between a conductive state and a non-conductive state by a voltage on a first signal line; and
a second unit including a second transistor arranged between the first terminal and the second terminal in correspondence with the first transistor of the first unit, wherein the second transistor can be controlled to change between a conductive state and a non-conductive state by a voltage on a second signal line,
wherein the voltage on the first signal line can be controlled independently of the voltage on the second signal line, a voltage on the first terminal, and a voltage on the second terminal, and
wherein the voltage on the second signal line can be controlled independently of the voltage on the first signal line, the voltage on the first terminal, and the voltage on the second terminal.

2. The device according to claim 1 , further comprising a resistive element configured to protect the plurality of units from electrostatic discharge (ESD).

3. The device according to claim 2 , wherein the plurality of units are arrayed such that, of the first unit and the second unit, the second unit has a shortest path to the resistive element.

4. The device according to claim 2 , wherein the plurality of units are arrayed such that, of the first unit and the second unit, the second unit has a longest path to the resistive element.

5. The device according to claim 2 , further comprising a rectifying element connected between the first terminal and the second terminal.

6. The device according to claim 2 , wherein between the first terminal and the second terminal, the second transistor functions as a protection transistor configured to protect the first unit from ESD.

7. The device according to claim 1 , wherein
the second unit further includes a Metal Oxide Silicon (MOS) structure corresponding to the memory element of the first unit, and
the first terminal and the second terminal are connected to the second transistor via a wiring portion, and the wiring portion is not connected to the MOS structure.

8. The device according to claim 1 , further comprising a controller configured to perform write to the memory element by controlling the voltage on the first signal line,
wherein the first unit is one of a plurality of first units, and
the controller performs write to a plurality of memory elements corresponding to the plurality of first units by a time division method.

9. The device according to claim 1 , wherein
the device is a print element substrate, and further comprises:
a plurality of print elements arrayed in the predetermined direction; and
a plurality of driving elements configured to drive the plurality of print elements.

10. A liquid discharge head comprising:
the device defined in claim 9 ; and
a plurality of liquid discharge ports corresponding to a plurality of print elements of the device.

11. The liquid discharge head according to claim 10 , wherein the device further comprises a resistive element configured to protect the plurality of units from electrostatic discharge (ESD).

12. The liquid discharge head according to claim 11 , wherein, in the device, the plurality of units are arrayed such that, of the first unit and the second unit, the second unit has a shortest path to the resistive element.

13. The liquid discharge head according to claim 11 , wherein, in the device, the plurality of units are arrayed such that, of the first unit and the second unit, the second unit has a longest path to the resistive element.

14. The liquid discharge head according to claim 10 , wherein
the second unit further includes a Metal Oxide Silicon (MOS) structure corresponding to the memory element of the first unit, and
the first terminal and the second terminal are connected to the second transistor via a wiring portion, and the wiring portion is not connected to the MOS structure.

15. The liquid discharge head according to claim 10 , wherein the device further comprises a controller configured to perform write to the memory element by controlling the voltage on the first signal line,
wherein the first unit is one of a plurality of first units, and
the controller performs write to a plurality of memory elements corresponding to the plurality of first units by a time division method.

16. The liquid discharge head according to claim 10 , wherein
the device is a print element substrate, and further comprises:
a plurality of print elements arrayed in the predetermined direction; and
a plurality of driving elements configured to drive the plurality of print elements.

17. A liquid discharge apparatus comprising:
the liquid discharge head defined in claim 10 ; and
a driver configured to drive the liquid discharge head.

18. The device according to claim 1 ,
wherein the first unit further includes a first inverter, wherein the first inverter controls the voltage on the first signal line, and
wherein the second unit further includes a second inverter, wherein the second inverter controls the voltage on the second signal line.

19. The device according to claim 18 ,
wherein the first inverter is controllable via a third signal line and a fourth signal line, and
wherein the second inverter is controllable via the third signal line and a fifth signal line.

20. The device according to claim 18 ,
wherein a structure of the first inverter is identical to a structure of the second inverter.

Assignees

• Canon Kk

Inventors

• Sakuma Sadayoshi
• Negishi Toshio
• Soeda Yasuhiro

Classifications

• H10B20/25

  One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links · CPC title

• B41J2/04541

  Specific driving circuit · CPC title

• B41J2/04511

  for electrostatic discharge protection · CPC title

• B41J2/0455

  Details of switching sections of circuit, e.g. transistors · CPC title

• G11C17/18

  Auxiliary circuits, e.g. for writing into memory · CPC title