Single-layered linear neural network based on cell synapse structure

Patent metadata

Field	Value
Publication number	US-12373679-B2
Application number	US-201917602804-A
Country	US
Kind code	B2
Filing date	Aug 7, 2019
Priority date	Apr 11, 2019
Publication date	Jul 29, 2025
Grant date	Jul 29, 2025

Abstract

A single-layered linear neural network based on a cell synapse structure comprising a pre-synapse and a post-synapse, the pre-synapse comprises a plurality of precursor resistors, number of the precursor resistors is m, one end of the precursor resistors in the pre-synapse is jointly connected with an intermediate point, and another end of the precursor resistors is respectively connected with each of a plurality of precursor signal input ends, number of the precursor signal input ends is m; the precursor signal input ends are used for receiving input voltages; the post-synapse comprises a plurality of posterior resistors, number of the precursor resistors is n, one end of the posterior resistors in the post-synapse is jointly connected with the intermediate point, and another end of the posterior resistors is respectively connected with each of a plurality of posterior signal output ends, number of the posterior signal output ends is n; the posterior signal output ends are used for outputting currents. The invention provides a single-layered linear neural network based on cell synapse structure, which can reduce the number of resistors; in addition, a weight between an external precursor neuron and an external posterior neuron can be changed only by adjusting two variable resistors or one of the two variable resistors.

First claim

What is claimed is:

1. A single-layered linear neural network circuit structure based on a cell synapse structure, comprising;
a pre-synapse circuit, and
a post-synapse circuit;
wherein the pre-synapse circuit comprises a plurality of precursor resistors, number of the precursor resistors is m, one end of each of the precursor resistors in the pre-synapse circuit is jointly connected with an intermediate point, and another end of each of the precursor resistors is respectively connected with each of a plurality of precursor signal input ends, number of the precursor signal input ends is m; the precursor signal input ends are used for receiving input voltages;
wherein the post-synapse circuit comprises a plurality of posterior resistors, number of posterior resistors is n, one end of each of the posterior resistors in the post-synapse circuit is jointly connected with the intermediate point, and another end of each of the posterior resistors is respectively connected with each of a plurality of posterior signal output ends, number of the posterior signal output ends is n; the posterior signal output ends are used for outputting currents; wherein, both of m and n are integers greater than one;
wherein the cell synapse structure of the pre-synapse and the post-synapse circuit of the single-layer linear neural network circuit represents a spike time dependent plasticity mechanism; and
wherein an increase in a weight, represented by a resistance value between one of the plurality of precursor resistors of the pre-synapse circuit and one of the plurality of posterior resistors of the post-synapse circuit, causes reduction in weights, represented by resistance values between the one precursor resistor of the pre-synapse circuit and the other remaining posterior resistors of the post-synapse circuit, as well as reduction in other weights, represented by resistance values between the one posterior resistor of the post-synapse circuit and the other remaining precursor resistors of the pre-synapse circuit.

2. The single-layered linear neural network circuit structure of claim 1 , wherein each of the precursor resistors is a variable resistor and each of the posterior resistors is a variable resistor.

3. The single-layered linear neural network circuit structure of claim 2 , wherein the precursor resistors are resistive random access memories and the posterior resistors are resistive random access memories.

4. The single-layered linear neural network circuit structure of claim 1 , a resistance relationship between the precursor resistors and the posterior resistors is adjusted to expand a weight adjustment threshold of the single-layered linear neural network.

5. The single-layered linear neural network circuit structure of claim 4 , wherein resistance values of the precursor resistors are all greater than resistance values of the posterior resistors.

6. The single-layered linear neural network circuit structure of claim 4 , wherein resistance values of the posterior resistors are all greater than resistance values of the precursor resistors.

7. The single-layered linear neural network circuit structure of claim 1 , wherein a method of varying a resistance value from a k-th precursor signal input end to an i-th posterior signal output end comprises: varying the resistance value of the k-th precursor resistor and/or the resistance value of the i-th posterior resistor, resistance values of the other precursor resistors and the other posterior resistors remain unchanged; wherein, k is an integer greater than 0 and less than or equal to m, i is an integer greater than 0 and less than or equal to n.

8. The single-layered linear neural network circuit structure of claim 1 , wherein further comprising a plurality of precursor neurons and a plurality of posterior neurons, number of the precursor neurons is m and number of the posterior neurons is n, each of the precursor neurons is respectively connected with each of the precursor signal input ends, and each of the posterior neurons is respectively connected with each of the posterior signal input ends.

9. The single-layered linear neural network circuit structure of claim 8 , wherein further comprising a plurality of precursor neuron circuits and a plurality of posterior neuron circuits, number of the precursor neuron circuits is m and number of the posterior neuron circuits is n, the precursor neuron circuits are corresponding to the precursor neurons, and the posterior neuron circuits are corresponding to the posterior neurons respectively; output ends of the posterior neuron circuits are jointly connected with the intermediate point and the precursor neuron circuits.

Assignees

• Shanghai Ic R&D Ct Co Ltd
• Shanghai Integrated Circuit Equipment & Mat Industry Innovation Center Co Ltd

Inventors

• Shen Ling
• Jiang Yu
• Yan Huijie
• Li Zhifang
• Wen Jianxin

Classifications

• G06N3/049

  Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs · CPC title

• G06N3/088

  Non-supervised learning, e.g. competitive learning · CPC title

• G06N3/063 Primary

  using electronic means · CPC title

• G06N3/065 Primary

  Analogue means · CPC title