Conditional branch instructions

Patent metadata

Field	Value
Publication number	US-12373216-B2
Application number	US-202418427411-A
Country	US
Kind code	B2
Filing date	Jan 30, 2024
Priority date	Aug 16, 2023
Publication date	Jul 29, 2025
Grant date	Jul 29, 2025

Abstract

Various embodiments of the present disclosure relate to conditional branch instructions to support software pipelining techniques. In an example embodiment, a system including instruction fetch circuitry, decoder circuitry, and conditional branch circuitry is provided. The instruction fetch circuitry is configured to fetch a conditional branch instruction from memory and provide the instruction to the decoder circuitry. The instruction includes an iteration count and multiple branch destinations. The branch destinations include two or more branch destinations corresponding to conditions against which the conditional branch circuitry evaluates the iteration count. The decoder circuitry is configured to cause the conditional branch circuitry to select a branch destination, of the two or more branch destinations, based on a comparison of the iteration count to each of the conditions and cause the instruction fetch circuitry to fetch an indication of an instruction from a memory location stored at the selected branch destination.

First claim

What is claimed is:

1. A system, comprising:
instruction fetch circuitry;
decoder circuitry coupled to the instruction fetch circuitry; and
conditional branch circuitry coupled to the decoder circuitry;
wherein the instruction fetch circuitry is configured to:
fetch a conditional branch instruction from a memory, wherein the conditional branch instruction specifies an iteration count and two or more branch destinations, corresponding to conditions against which the conditional branch circuitry evaluates the iteration count; and
provide the conditional branch instruction to the decoder circuitry; and

wherein the decoder circuitry is configured to cause the conditional branch circuitry to:
select a branch destination, of the two or more branch destinations, based on a comparison of the iteration count to each of the conditions; and
cause the instruction fetch circuitry to fetch an indication of an instruction from a memory location stored at the selected branch destination.

2. The system of claim 1 , wherein the decoder circuitry is further configured to cause the conditional branch circuitry to perform the comparison of the iteration count to each of the conditions, wherein each condition of the conditions corresponds to a branch destination of the two or more branch destinations.

3. The system of claim 1 , wherein the iteration count is based on a number of remainder operations resulting after performing a loop instruction a number of times.

4. The system of claim 3 , wherein the instruction fetch circuitry is further configured to fetch the loop instruction from the memory and provide the loop instruction to the decoder circuitry.

5. The system of claim 4 , wherein the decoder circuitry is further configured to cause conditional branch circuitry to perform the loop instruction the number of times and the conditional branch circuitry to decrement the iteration count each time the conditional branch circuitry performs the loop instruction.

6. The system of claim 1 , wherein the conditional branch instruction further identifies a field.

7. The system of claim 1 , wherein the instruction at the memory location stored at the selected branch destination corresponds to a number of remainder operations.

8. The system of claim 1 , further comprising the memory.

9. One or more computer-readable storage media, comprising:
program instructions stored thereon comprising a conditional branch instruction that specifies an iteration count and two or more branch destinations corresponding to conditions against which a processor evaluates the iteration count, wherein the program instructions, when read and executed by a processing system, direct the processor to:
select a branch destination, of the two or more branch destinations, based on a comparison of the iteration count to each of the conditions; and
fetch an indication of an instruction from a memory location stored at the selected branch destination.

10. The one or more computer-readable storage media of claim 9 , wherein the program instructions further direct the processor to perform the comparison of the iteration count to each of the conditions, wherein each condition of the conditions corresponds to a branch destination of the two or more branch destinations.

11. The one or more computer-readable storage media of claim 9 , wherein the iteration count is based on a number of remainder operations resulting after performing a loop instruction a number of times.

12. The one or more computer-readable storage media of claim 11 , wherein the program instructions further comprise a loop instructions.

13. The one or more computer-readable storage media of claim 12 , wherein the program instructions further direct the processor to perform the loop instruction the number of times and decrement the iteration count each time the loop instruction is performed.

14. The one or more computer-readable storage media of claim 9 , wherein the conditional branch instruction further identifies a field.

15. The one or more computer-readable storage media of claim 9 , wherein the instruction at the memory location stored at the selected branch destination corresponds to a number of remainder operations.

16. A method, comprising:
receiving, instruction fetch circuitry, a conditional branch instruction from memory;
performing a comparison of an iteration count specified by the conditional branch instruction to each of multiple conditions corresponding to two or more branch destinations specified by the conditional branch instruction;
selecting a branch destination, of the two or more branch destinations, based on the result of the comparison; and
causing the instruction fetch circuitry to fetch an indication of an instruction from a memory location stored at the selected branch destination.

17. The method of claim 16 , wherein the iteration count is based on a number of remainder operations resulting after performing a loop instruction a number of times.

18. The method of claim 17 , further comprising receiving, via the instruction fetch circuitry, the loop instruction from the memory.

19. The method of claim 18 , further comprising:
performing the loop instruction the number of times; and
decrementing the iteration count each time the loop instruction is performed.

20. The method of claim 16 , wherein the instruction at the memory location stored at the selected branch destination corresponds to a number of remainder operations.

Assignees

• Texas Instruments Inc

Inventors

• Tessarolo Alexander
• Natarajan Venkatesh
• Davis Alan

Classifications

• G06F9/30061

  Multi-way branch instructions, e.g. CASE · CPC title

• G06F9/323

  for indirect branch instructions · CPC title

• G06F9/30058 Primary

  Conditional branch instructions · CPC title

• G06F9/325

  for loops, e.g. loop detection or loop counter · CPC title

• G06F9/3804 Primary

  for branches, e.g. hedging, branch folding · CPC title