Spliced display screen reducing hashrate of inner processing algorithm

US12373154B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12373154-B2
Application numberUS-202318695816-A
CountryUS
Kind codeB2
Filing dateJul 31, 2023
Priority dateSep 7, 2022
Publication dateJul 29, 2025
Grant dateJul 29, 2025

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  1. Title

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  2. Abstract

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  5. First independent claim

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Abstract

Official abstract text for this publication.

Provided is a spliced display screen. The spliced display screen includes a plurality of display screen modules, a plurality of control modules, and a communication bus; an image processing algorithm is configured in each control module; the each of the plurality of control modules is configured to receive video information and send an edge signal supplement request to other control modules; determine whether the communication bus is occupied by the each of the plurality of control modules; determine the each of the plurality of control modules as a master control module and other control modules as slave control modules; read at least part of edge information via the communication bus; and perform imaging processing on the received video information and multiple pieces of the at least part of edge information to generate image sub-information; and the plurality of display screen modules are configured to display received image sub-information.

First claim

Opening claim text (preview).

The invention claimed is: 1. A spliced display screen, comprising: a plurality of display screen modules spliced with each other, a plurality of control modules, and a communication bus; wherein one of the plurality of display screen modules corresponds to one of the plurality of control modules, an image processing algorithm is configured in each of the plurality of control modules, and the plurality of control modules are communicably connected via the communication bus; the each of the plurality of control modules is configured to: send an edge signal supplement request to other control modules in the spliced display screen in response to received video information, wherein the edge signal supplement request carries address information of at least part of other control modules than the each of the plurality of control modules; determine, based on the address information, whether the communication bus is occupied by the each of the plurality of control modules; determine the each of the plurality of control modules as a master control module and other control modules corresponding to the address information occupying the communication bus as slave control modules in response to the communication bus being occupied by the each of the plurality of control modules; read at least part of edge information of the video information received by the slave control modules via the communication bus in response to acquiring a control right over the communication bus; release control over the communication bus for a new occupation of the communication bus among the other control modules; and perform imaging processing on the received video information and multiple pieces of the at least part of edge information in response to reading the multiple pieces of the at least part of edge information from the at least part of other control modules, such that image sub-information for displaying is generated; and the plurality of display screen modules are configured to display received image sub-information; and wherein in a case that the communication bus is occupied by a plurality of master control modules simultaneously, each of the plurality of master control modules is further configured to determine whether the each of the plurality of master control modules has the control right over the communication bus; the each of the plurality of master control modules comprises a determining unit and a reading unit; wherein the determining unit is configured to send preconfigured reading codes to the slave control modules, and determine, based on the reading codes, whether the each of the plurality of master control modules has the control right over the communication bus; and the reading unit is configured to send an information read request to the slave control modules in response to the each of the plurality of master control modules having the control right over the communication bus, and read the at least part of edge information fed back from the slave control modules via the communication bus; and release the control over the communication bus for the new occupation of the communication bus among the other control modules; each of the slave control modules comprises a receiving unit and a sending unit; wherein the receiving unit is configured to determine the at least part of edge information of the received video information in response to the received reading codes; and the sending unit is configured to send the at least part of edge information to the reading unit in response to the received information read request. 2. The spliced display screen according to claim 1 , wherein the determining unit is configured to sequentially send data bits of the reading codes to the communication bus, and determine whether a logic level of a currently-sent data bit is coincident with a logic level of the communication bus at a current time each time one of the data bits is sent; and determine that the each of the plurality of master control modules has the control right over the communication bus in response to the logic level of the currently-sent data bit being coincident with the logic level of the communication bus at the current time and the logic level of the currently-sent data bit being a low level. 3. The spliced display screen according to claim 1 , wherein the each of the plurality of control modules is configured to sequentially send data bits of the address information to the communication bus, and determine that the communication bus is occupied by the each of the plurality of control modules in response to a currently-sent data bit being a low level and a logic level of the communication bus being adjusted to the low level; and the communication bus is configured to adjust the logic level of the communication bus to the low level in response to a logic level of a data bit of the received address information sent by any of the plurality of control modules being the low level. 4. The spliced display screen according to claim 1 , wherein the edge signal supplement request carries at least one data byte, wherein a first bit of the data byte is configured to represent a data bit of read control or write control; each of the slave control modules is configured to detect, in response to the edge signal supplement request and a received first data bit being a write control bit, whether the received address information is coincident with predetermined address information; and feed back a response signal to the each of the plurality of master control modules in response to the received address information being coincident with the predetermined address information; and the each of the plurality of master control modules is configured to receive the response signal from the each of the slave control modules, and read, in response to acquiring the control right over the communication bus, part of edge information of the video information received by the slave control modules via the communication bus; and release the control over the communication bus. 5. The spliced display screen according to claim 1 , wherein the each of the plurality of control modules further comprises a clock unit, wherein an initial state of a logic level of the clock unit is a high level state; the communication bus comprises a data signal line and a clock signal line, wherein an initial state of a logic level of the clock signal line is the high level state; the clock unit is configured to detect the logic level of the clock signal line; adjust the logic level in the high level state to a low level in response to a shift of the logic level of the clock signal line from the high level to the low level, and adjust the logic level in a low level state to the high level upon maintaining of the low level state for a predetermined low level period; adjust the clock signal line to be in a high level waiting state in response to the logic level of the clock signal line being maintained at the low level state; count high level periods of the clock signal line in response to a shift of the logic level of the clock signal line from the low level to the high level, and adjust the logic level of the clock signal line in the high level state to the low level in response to the high level periods of the clock signal line being less than high level periods of the clock unit of any of the other control modules; and the clock signal line is configured to detect logic levels of the clock units of the plurality of control modules in response to the shift of the logic level of the clock signal line from the high level to the low level and maintaining of the logic level of the clock signal line at the low level state; and adjust the logic level of the clock signal line to the high level in response to the logic levels of the clock units of the plurality of control mod

Assignees

Inventors

Classifications

  • Digital output to display device {; Cooperation and interconnection of the display device with other functional units} · CPC title

  • G06F3/1446Primary

    display composed of modules, e.g. video walls · CPC title

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Frequently asked questions

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What does patent US12373154B2 cover?
Provided is a spliced display screen. The spliced display screen includes a plurality of display screen modules, a plurality of control modules, and a communication bus; an image processing algorithm is configured in each control module; the each of the plurality of control modules is configured to receive video information and send an edge signal supplement request to other control modules; de…
Who is the assignee on this patent?
Boe Technology Group Co Ltd
What technology area does this patent fall under?
Primary CPC classification G06F3/1446. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jul 29 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).