Front-end electronic circuitry for a photon counting application

Patent metadata

Field	Value
Publication number	US-12372669-B2
Application number	US-202118251784-A
Country	US
Kind code	B2
Filing date	Nov 3, 2021
Priority date	Nov 12, 2020
Publication date	Jul 29, 2025
Grant date	Jul 29, 2025

Abstract

A front-end electronic circuitry for a photon counting application includes a charge sensitive amplifier including an amplifier circuit and a capacitor being arranged in a feedback path between the input side and the output side of the amplifier circuit. A controllable switch is arranged in parallel to the capacitor. The circuitry includes a delay circuit to provide a delay circuit output signal being a time-delayed representation of the charge sensitive amplifier output signal. An output signal generation circuit is configured to generate the output signal by subtracting the delay circuit output signal from the charge sensitive amplifier output signal.

First claim

The invention claimed is:

1. A front-end electronic circuitry for a photon counting application, comprising:
an output node to provide an output signal,
an input node to receive a input signal,
a charge sensitive amplifier comprising an amplifier circuit having an input side being coupled to the input node and an output side to provide a charge sensitive amplifier output signal, and a capacitor being arranged in a feedback path between the input side and the output side of the amplifier circuit,
a controllable switch being arranged in parallel to the capacitor,
a delay circuit to provide a delay circuit output signal, the delay circuit output signal being a time-delayed representation of the charge sensitive amplifier output signal,
an output signal generation circuit being coupled to the output node to provide the output signal,
wherein the output signal generation circuit is configured to generate the output signal by subtracting the delay circuit output signal from the charge sensitive amplifier output signal.

2. The front-end electronic circuitry of claim 1 ,
wherein the delay circuit has an input side to receive the charge sensitive amplifier output signal,
wherein the delay circuit is configured to generate the delay circuit output signal with a first delay time after having received the charge sensitive amplifier output signal at the input side of the delay circuit.

3. The front-end electronic circuitry of claim 1 ,
wherein the charge sensitive amplifier and the capacitor are arranged so that, when the input signal is formed as a current pulse, a charge is stored in the capacitor, the charge being dependent on the current pulse of the input signal.

4. The front-end electronic circuitry of claim 1 ,
wherein the controllable switch is operated in a non-conductive state and a conductive state,
wherein the controllable switch and the capacitor are arranged so that the capacitor is charged, when the controllable switch is operated in the non-conductive state, and the capacitor is discharged, when the controllable switch is operated in the conductive state.

5. The front-end electronic circuitry of claim 1 , comprising:
a control circuit being configured to monitor the charge stored in the capacitor and to control the controllable switch in dependence on the charge stored in the capacitor.

6. The front-end electronic circuitry of claim 5 ,
wherein the control circuit is configured to switch the controllable switch from the non-conductive state in the conductive state after a delay, when the control circuit detects that the charge stored in the capacitor exceeds a threshold value.

7. The front-end electronic circuitry of claim 5 ,
wherein the control circuit comprises a second delay circuit to generate a control signal to switch the controllable switch from the non-conductive state in the conductive state,
wherein the second delay circuit is configured to generate the control signal with a second delay time after the control circuit has detected the exceeding of a threshold value of the charge stored in the capacitor.

8. The front-end electronic circuitry of claim 7 ,
wherein the delay circuit and the second delay circuit are configured such that the second delay time is shorter than or equal to the first delay time.

9. The front-end electronic circuitry of claim 1 comprising:
a second controllable switch to disconnect the delay circuit from the output signal generation circuit,
wherein the output signal generation circuit has a first input connected to the second controllable switch and a second input connected to the output side of the charge sensitive amplifier circuit.

10. The front-end electronic circuitry of claim 9 ,
wherein the second controllable switch is configured to be operated in a first state in which the second controllable switch connects the delay circuit to the first input of the output signal generation circuit, and a second state in which the second controllable switch disconnects the delay circuit from the first input node of the output signal generation circuit, and connects the first input node of the output signal generation circuit to a reference potential.

11. The front-end electronic circuitry of claim 9 ,
wherein the control circuit comprises a control stage to generate a second control signal with a first level to switch the second controllable switch from the first state to the second state, and with a second level to switch the second controllable switch from the second state to the first state,
wherein the control stage is configured to generate the first level of the second control signal with a third delay time after having generated the second level of the second control signal.

12. The front-end electronic circuitry of claim 11 ,
wherein the third delay circuit is configured such that the third delay time is equal or longer than the second delay time.

13. The front-end electronic circuitry of claim 1 ,
wherein the integrator circuit comprises a resistor being connected in parallel to the capacitor.

14. A photon counting circuitry, comprising:
a front-end electronic circuitry according to claim 1 ,
a photon detector having a photon sensitive area, the photon detector being configured to generate a current pulse, when a photon hits the photon sensitive area,
an energy discriminator being connected to the output node of the front-end electronic circuitry,
wherein the photon detector is connected to the input node of the front-end electronic circuitry so that the current pulse generated by the photon detector circuitry is applied to the input node of the front-end electronic circuitry, when the photon hits the photo sensitive area of the photon detector,
wherein the front-end electronic circuitry is configured to generate a voltage pulse at the output node of the front-end electronic circuitry, when the current pulse is applied to the input node of the front-end electronic circuitry,
wherein the energy discriminator is configured to generate a digital signal in dependence on a level of the voltage pulse.

15. A device for medical diagnostics, comprising:
the photon counting circuitry of claim 14 ,
wherein the device is configured as an X-ray apparatus or a computer tomography.

Assignees

• Ams Int Ag
• Ams Sensors Singapore Pte Ltd

Inventors

• Michel Fridolin
• Andreou Charalambos
• Rigo Massimo
• Steiner Matthias
• Gavillero Juan Miguel

Classifications

• A61B6/4241

  using energy resolving detectors, e.g. photon counting · CPC title

• G01T1/20 Primary

  with scintillation detectors · CPC title

• G01T1/171 Primary

  Compensation of dead-time counting losses · CPC title