Semiconductor integrated circuit device

Patent metadata

Field	Value
Publication number	US-12369405-B2
Application number	US-202217877534-A
Country	US
Kind code	B2
Filing date	Jul 29, 2022
Priority date	Feb 10, 2020
Publication date	Jul 22, 2025
Grant date	Jul 22, 2025

Abstract

In a semiconductor integrated circuit device, first and second IO cell rows are placed in an IO region on a chip. IO cells in the first IO cell row are larger in plane area than IO cells in the second IO cell row. Pads connected to the IO cells in the first IO cell row are located closer to an outer edge of the chip than any pads connected to the IO cells in the second IO cell row.

First claim

What is claimed is:

1. A semiconductor integrated circuit device, comprising:
a chip;
a core region provided on the chip;
an IO region provided on the chip between the core region and an outer edge of the chip;
a first IO cell row placed in the IO region, including at least two IO cells arranged in a first direction that is a direction along the outer edge;
a second IO cell row placed in the IO region, including at least two IO cells arranged in the first direction, located between the first IO cell row and the outer edge; and
a plurality of pads formed on a surface of the chip, individually connected to the IO cells in the first and second IO cell rows and electrically connected to the outside of the semiconductor integrated circuit device,

wherein
the IO cells in the first IO cell row are larger in plane area than the IO cells in the second IO cell row, and
the pads connected to the IO cells in the first IO cell row are located closer to the outer edge than any of the pads connected to the IO cells in the second IO cell row.

2. The semiconductor integrated circuit device of claim 1 , further comprising:
a third IO cell row placed in the IO region, including at least two IO cells arranged in the first direction, located between the second IO cell row and the outer edge or located closer to the core region than the first IO cell row.

3. A semiconductor integrated circuit device, comprising:
a chip;
a core region provided on the chip;
an IO region provided on the chip, between the core region and an outer edge of the chip;
a first IO cell row placed in the IO region, including at least two IO cells arranged in a first direction that is a direction along the outer edge;
a second IO cell row placed in the IO region, including at least two IO cells arranged in the first direction, located between the first IO cell row and the outer edge; and
a plurality of pads formed on a surface of the chip, individually connected to the IO cells in the first and second IO cell rows and electrically connected to the outside of the semiconductor integrated circuit device,

wherein
the IO cells in the first IO cell row are larger in plane area than the IO cells in the second IO cell row, and
when the plurality of pads are divided into a first pad group and a second pad group closer to the outer edge than the first pad group, the first pad group includes pads connected to the IO cells in the second IO cell row in larger number than pads connected to the IO cells in the first IO cell row, and the second pad group includes pads connected to the IO cells in the first IO cell row in larger number than pads connected to the IO cells in the second IO cell row.

4. The semiconductor integrated circuit device of claim 3 , further comprising:
a third IO cell row placed in the IO region, including at least two IO cells arranged in the first direction, located between the second IO cell row and the outer edge or located closer to the core region than the first IO cell row.

5. A semiconductor integrated circuit device, comprising:
a chip;
a core region provided on the chip;
an IO region provided on the chip, between the core region and an outer edge of the chip;
a first IO cell row placed in the IO region, including at least two IO cells arranged in a first direction that is a direction along the outer edge;
a second IO cell row placed in the IO region, including at least two IO cells arranged in the first direction, located between the first IO cell row and the outer edge; and
a plurality of pads formed on a surface of the chip, individually connected to the IO cells in the first and second IO cell rows and electrically connected to the outside of the semiconductor integrated circuit device,

wherein
the IO cells in the first IO cell row are larger in plane area than the IO cells in the second IO cell row, and
at least one IO cell in the first IO cell row is connected to a pad of the plurality of pads located closer to the outer edge than the IO cell itself, and at least one IO cell in the second IO cell row is connected to a pad of the plurality of pads located farther from the outer edge than the IO cell itself.

6. The semiconductor integrated circuit device of claim 5 , further comprising:
a third IO cell row placed in the IO region, including at least two IO cells arranged in the first direction, located between the second IO cell row and the outer edge or located closer to the core region than the first IO cell row.

Assignees

• Socionext Inc

Inventors

• Fukunaga Taro
• Iida Masahisa
• Nakamura Toshihiro

Classifications

• H10W72/9445

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W70/656

  Fan-in layouts · CPC title

• H10W70/654

  Top-view layouts · CPC title

• H10W72/248

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W72/90 Primary

  Bond pads, in general · CPC title