Manufacturing method of semiconductor structure and semiconductor structure

Patent metadata

Field	Value
Publication number	US-12369296-B2
Application number	US-202117599695-A
Country	US
Kind code	B2
Filing date	Jun 11, 2021
Priority date	Aug 5, 2020
Publication date	Jul 22, 2025
Grant date	Jul 22, 2025

Abstract

The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method includes: providing a substrate, where the substrate includes a complete die region and an incomplete die region; forming a stack on the substrate, where the stack includes sacrificial layers and supporting layers; forming a first photoresist layer on the stack; exposing the first photoresist layer, and developing to remove the first photoresist layer on the incomplete die region; and etching the stack by using the first photoresist layer on the complete die region as a mask.

First claim

The invention claimed is:

1. A manufacturing method of a semiconductor structure, wherein the manufacturing method of the semiconductor structure comprises:
providing a substrate, wherein the substrate comprises a complete die region and an incomplete die region; the complete die region is composed of complete dies inside the substrate, and the incomplete die region is composed of incomplete dies at the periphery of the substrate, the incomplete die region is located at the periphery of the complete die region, the complete die is a die that is completely on the substrate, the incomplete die is a die that is partially on the substrate;
forming a stack on the substrate, wherein the stack comprises sacrificial layers and supporting layers;
forming a first photoresist layer on the stack, wherein the first photoresist layer is a positive photoresist layer;
exposing the first photoresist layer, wherein the first photoresist layer on the incomplete die region is exposed by using a step exposure method and developing to remove the first photoresist layer on the incomplete die region; and
etching the stack by using the first photoresist layer on the complete die region as a mask;
wherein the manufacturing method of the semiconductor structure further comprises:
forming a first mask layer on the stack, wherein the first photoresist layer is located on the first mask layer;
etching the first mask layer by using the first photoresist layer on the complete die region as a mask; and
etching the stack by using the first mask layer as a mask.

2. The manufacturing method according to claim 1 , wherein the step exposure method is carried out without using a photomask, and a light spot in the step exposure method at least covers a single complete die.

3. The manufacturing method according to claim 2 , wherein an area of the light spot in the step exposure method is smaller than an area of a single exposure unit.

4. The manufacturing method according to claim 1 , wherein a light spot in the step exposure method exactly completely covers a single complete die.

5. The manufacturing method according to claim 1 , wherein the exposing the first photoresist layer comprises:
exposing the first photoresist layer on the complete die region, and developing to form a first pattern on the first photoresist layer on the complete die region; and
exposing the first photoresist layer on the incomplete die region, and developing to remove the first photoresist layer on the incomplete die region.

6. The manufacturing method according to claim 5 , wherein
an exposure of the first photoresist layer on the incomplete die region is carried out before the exposing the first photoresist layer on the complete die region.

7. The manufacturing method according to claim 5 , wherein
the first photoresist layer on the complete die region is exposed by using a photomask, and the first photoresist layer on the incomplete die region is exposed without using a photomask.

8. The manufacturing method according to claim 5 , wherein
the first photoresist layer on the complete die region is exposed by using an immersion lithography machine or an extreme ultraviolet lithography machine;
the first photoresist layer on the incomplete die region is exposed by using an I-line lithography machine or a KrF lithography machine.

9. The manufacturing method according to claim 5 , wherein the manufacturing method further comprises:
etching to transfer the first pattern of the complete die region to the first mask layer and remove the first mask layer on the incomplete die region.

10. The manufacturing method according to claim 9 , wherein the manufacturing method further comprises:
forming a second photoresist layer on the first mask layer having the first pattern; and
exposing the second photoresist layer, and developing to form a second pattern on the second photoresist layer on the complete die region and remove the second photoresist layer on the incomplete die region.

11. The manufacturing method according to claim 10 , wherein the manufacturing method further comprises:
etching the stack by using the first pattern and the second pattern as a mask to form capacitor holes in the stack; and
forming bottom electrodes on bottoms and sidewalls of the capacitor holes.

12. The manufacturing method according to claim 11 , wherein after the forming bottom electrodes on bottoms and sidewalls of the capacitor holes, the manufacturing method further comprises:
forming a third photoresist layer on the stack in the stack the capacitor holes are formed; and
forming a third pattern on the third photoresist layer;
wherein, the third pattern at least intersects the bottom electrodes on the sidewalls of the capacitor holes.

13. The manufacturing method according to claim 10 , wherein the second photoresist layer is a positive photoresist layer or a negative photoresist layer.

14. A semiconductor structure, formed by the manufacturing method of a semiconductor structure according to claim 1 .

Assignees

• Changxin Memory Tech Inc

Inventors

• Xia Jun
• Liu Tao
• Wan Qiang
• Kang Jungsu
• Zhan Kangshu
• Li Sen

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P76/2041

  Photolithographic processes · CPC title

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10B12/09 Primary

  with simultaneous manufacture of the peripheral circuit region and memory cells · CPC title