Optical transmitter with encoder encoding processed data including concatenating parity bits to generate fec data blocks

Patent metadata

Field	Value
Publication number	US-12368528-B2
Application number	US-202318384267-A
Country	US
Kind code	B2
Filing date	Oct 26, 2023
Priority date	Aug 30, 2017
Publication date	Jul 22, 2025
Grant date	Jul 22, 2025

Abstract

A transmitter includes: an input configured to receive, via an electrical interface, encoded data from a host device, the encoded data being encoded at the host device according to a first code; processing circuitry configured to process the encoded data to provide processed data; an encoder configured to encode the processed data according to a second code that is different than the first code, where encoding the processed data includes concatenating one or more parity bits to the processed data to provide forward error correction (FEC) blocks of data; and transmit circuitry to transmit the FEC data over an optical medium.

First claim

What is claimed is:

1. A transmitter comprising:
an input configured to receive, via an electrical interface, encoded data from a host device, the encoded data being encoded at the host device according to a first code;
processing circuitry configured to process the encoded data to provide processed data;
an encoder configured to encode the processed data according to a second code that is different than the first code, wherein encoding the processed data includes concatenating one or more parity bits to the processed data to provide forward error correction (FEC) blocks of data; and
transmit circuitry to transmit the FEC blocks of data over an optical medium.

2. The transmitter of claim 1 , wherein the encoder is configured to encode the processed data includes concatenating two or more parity bits to the processed data to provide the FEC blocks of data, the two or more parity bits including the one or more parity bits.

3. The transmitter of claim 2 , wherein:
the processing circuitry comprises an interleaver configured to interleave the received encoded data to provide interleaved data;
the encoder is configured to concatenate the parity bits to the interleaved data to provide the FEC blocks of data; and
the processed data includes the interleaved data.

4. The transmitter of claim 2 , wherein:
the processing circuitry is configured to amplitude modulate the received encoded data to provide amplitude modulated data;
the encoder is configured to concatenate the parity bits to the amplitude modulated data to provide the FEC blocks of data; and
the processed data includes the amplitude modulated data.

5. The transmitter of claim 2 , wherein:
the processing circuitry is configured to split the received encoded data into even blocks of data and odd blocks of data, a block of data is deemed an even block of data or an odd block of data based on a serial number of the block of data;
the encoder is configured to concatenate the two or more parity bits to the even blocks of data and the odd blocks of data to provide the FEC blocks of data; and
the processed data includes the even blocks of data and the odd blocks of data.

6. The transmitter of claim 5 , further comprising an interleaver configured to interleave the even blocks of data, interleave the odd blocks of data, and interleave the even blocks of data with the odd blocks of data to provide interleaved data,
wherein the encoder is configured to concatenate the two or more parity bits to the interleaved data to provide the FEC blocks of data, and wherein the processed data includes the interleaved data.

7. The transmitter of claim 1 , further comprising a first interleaver configured to interleave portions of first blocks of the received encoded data to provide a first series of interleaved data blocks, each of the interleaved data blocks in the first series of interleaved data blocks including portions of two of the first blocks of the encoded data,
wherein the encoder is configured to concatenate to each of the interleaved data blocks in the first series of interleaved data blocks a respective one of the parity bits to provide a respective one of the FEC blocks of data.

8. The transmitter of claim 7 , wherein:
the first interleaver is configured to interleave portions of the received encoded data to provide the first series of interleaved data blocks comprising a first interleaved data block and a second interleaved data block;
the first blocks of the received encoded data comprise a first block of data and a second block of data;
the first interleaved data block comprises a first portion of the first block of data and a first portion of the second block of data; and
the second interleaved data block comprises a second portion of the first block of data and a second portion of the second block of data.

9. The transmitter of claim 8 , wherein the encoder is configured to concatenate a first parity bit to the first interleaved data block and concatenate a second parity bit to the second interleaved data block.

10. The transmitter of claim 7 , further comprising a second interleaver configured to interleave portions of second blocks of the received encoded data to provide a second series of interleaved data blocks, each of the interleaved data blocks in the second series of interleaved data blocks including portions of two of the second blocks of the received encoded data,
wherein the encoder is configured to concatenate to each of the interleaved data blocks in the second series of interleaved data blocks a respective one of the parity bits to provide a respective one of the FEC blocks of data.

11. The transmitter of claim 1 , wherein the encoder is configured to encode the processed data according to a second code to increase coding gain.

12. The transmitter of claim 1 , wherein:
the input is configured to receive, via the electrical interface, encoded codewords from the host device, the encoded codewords being encoded at the host device according to the first code,
the received encoded data includes the encoded codewords; and
the processing circuitry is configured to process the encoded codewords to provide the processed data.

13. The transmitter of claim 12 , wherein:
the processing circuitry comprises an interleaver configured to interleave the encoded codewords to provide interleaved data;
the encoder is configured to concatenate the parity bits to the interleaved data to provide the FEC blocks of data; and
the processed data includes the interleaved data.

14. The transmitter of claim 12 , wherein:
the processing circuitry is configured to amplitude modulate the encoded codewords to provide amplitude modulated data;
the encoder is configured to concatenate the parity bits to the amplitude modulated data to provide the FEC blocks of data; and
the processed data includes the amplitude modulated data.

15. The transmitter of claim 12 , wherein:
the processing circuitry is configured to split the encoded codewords into even blocks of data and odd blocks of data;
the encoder is configured to concatenate the parity bits to the even blocks of data and the odd blocks of data to provide the FEC blocks of data; and
the processed data includes the even blocks of data and the odd blocks of data.

16. The transmitter of claim 15 , further comprising a first interleaver configured to interleave the even blocks of data and the odd blocks of data to provide interleaved data,
wherein the encoder is configured to concatenate the parity bits to the interleaved data to provide the FEC blocks of data, and wherein the processed data includes the interleaved data.

17. The transmitter of claim 12 , further comprising a first interleaver configured to interleave portions of first ones of the encoded codewords to provide a first series of interleaved data blocks, each of the interleaved data blocks in the first series of interleaved data blocks including portions of two of the first ones of the encoded codewords,
wherein the encoder is configured to concatenate to each of the interleaved data blocks in the first series of interleaved data blocks a respective one of the parity bits to provide a respective one of the FEC blocks of data.

18. The transmitter of claim 17 , wherein:
the first interleaver is configured to interleave portions of the encoded codewords to provide the first series of interleaved data blocks comprising a first interleaved data block and a second interleaved data block;
the encoded codewords comprise a first codeword and a second codeword;
the first inte

Assignees

• Marvell Asia Pte Ltd

Inventors

• Riani Jamal
• Smith Benjamin
• Shvydun Volodymyr
• Bhoja Sudeep
• Farhoodfar Arash

Classifications

• H03M13/1515

  Reed-Solomon codes · CPC title

• H04L1/0058

  Block-coded modulation · CPC title

• H03M13/2906

  using block codes (H03M13/2957 takes precedence) · CPC title

• H04B14/023

  using pulse amplitude modulation · CPC title

• H04L2001/0096

  Channel splitting in point-to-point links · CPC title