Power semiconductor module having a substrate, power semiconductor components and having a DC voltage connection device

US12368385B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12368385-B2
Application numberUS-202217735014-A
CountryUS
Kind codeB2
Filing dateMay 2, 2022
Priority dateMay 12, 2021
Publication dateJul 22, 2025
Grant dateJul 22, 2025

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  1. Title

    What the patent document calls the invention.

  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A power semiconductor module has a substrate that has an electrically non-conductive insulating layer and a first metal layer on the insulating layer and forms conductor tracks, with power semiconductor components arranged on the first metal layer and electrically connected to the first metal layer and having a DC voltage connection device that has a first, second and third flat conductor connection element that are arranged on an end region of the power semiconductor module and that are electrically conductively connected to the first metal layer. During operation, the first and second flat conductor connection elements have a first electrical polarity and the third flat conductor connection element has a second electrical polarity.

First claim

Opening claim text (preview).

What is claimed is: 1. A power semiconductor module, comprising: a substrate that has an electrically non-conductive insulating layer and a first metal layer arranged on a first side of the insulating layer and said first metal layer is structured to form a plurality of respective conductor tracks spaced apart from each other, a second metal layer that is arranged a second side of the insulating layer opposite from said first metal layer; a plurality of power semiconductor components arranged on the first metal layer and electrically conductively connected to the first metal layer at respective ones of said respective conductor tracts; a DC voltage connection device has a first, a second and a third flat conductor connection element that are arranged on an end region (E) of the power semiconductor module and that are electrically conductively connected to the first metal layer; wherein, during an operation of the power semiconductor module, the first and second flat conductor connection element have a first electrical polarity and the third flat conductor connection element has a second electrical polarity that is an opposite polarity from said first electrical polarity; the first and the second flat conductor connection elements extend in part over respectively a first plane (E 1 ) that is parallel to said substrate; wherein the DC voltage connection device has a flat conductor connecting element that runs over the first plane (E 1 ) between the first and second flat conductor connection element and that electrically conductively connects the first and second flat conductor connection element to one another, the first and the second flat conductor connection elements and the flat connecting element are formed as a unitary one piece with one another; the third flat conductor connection element extends in part over a second plane (E 2 ) above said flat connecting element; an electrically non-conductive insulating layer is arranged between the flat conductor connecting element and the third flat conductor connection element; the second plane (E 2 ) is arranged at a distance from the first plane (E 1 ) in a normal direction (N 1 ) of the first plane (E 1 ) wherein the second plane (E 2 ) is arranged above the first plane (E 1 ) and away from substrate; said respective normal direction (N 1 ) of said first plane (E 1 ) matches a respective normal direction (N 2 ) of the second plane (E 2 ); said first and said second flat conductor connection elements and said third flat conductor connection element each arranged above said first metal layer along said normal direction (N 1 ); the third flat conductor connection element is arranged in part along said second plane (E 2 ), in a location that is both between and spaces apart the first and second flat conductor connection element and is elevated in a projection in the normal direction (N 1 ) above the first plane (E 1 ); whereby said first, said second and said third flat conductor connection element that are arranged on said end region (E) of the power semiconductor module and that are electrically conductively connected to the first metal layer each have respective connection portions that extend from respective first, second, and third flat conductor connection elements in said respective normal direction (N 1 ) to said first metal layer above said substrate. 2. The power semiconductor module, according to claim 1 , wherein: the insulating layer is formed from a plastic selected from a group of plastics consisting of polyimide, ethylene-tetrafluoroethylene copolymer, and liquid crystal polymer; and the insulating layer bas thickness of 50 μm to 500 μm. 3. The power semiconductor module, according to claim 1 , wherein: the flat conductor connecting element is in the form of a metal foil or metal sheet; and the flat conductor has a thickness (D 4 ) of 300 μm to 2000 μm. 4. The power semiconductor module, according to claim 3 , wherein: the first, second and third flat conductor connection element are each in the form of a metal foil or metal sheet; and each said flat conductor connection element has a thickness (D 1 , D 2 , D 3 ) of 300 μm to 2000 μm. 5. The power semiconductor module, according to claim 4 , wherein: the respective flat conductor connection element runs in a common direction, running perpendicular to the normal direction (N 3 ) of the insulating layer, and away from the substrate. 6. A power electronics arrangement, comprising: a power semiconductor module according to claim 1 ; further comprising: having a DC voltage busbar that has a first and a second flat conductor and an electrically non-conductive insulating layer arranged between the first and the second flat conductor; the first flat conductor has a first and a second flat conductor connection and the second flat conductor has a third flat conductor connection; the first flat conductor connection is in electrically conductive contact with the first flat conductor connection element, the second flat conductor connection is in electrically conductive contact with the second flat conductor connection element and the third flat conductor connection is in electrically conductive contact the third flat conductor connection element, by way of a respective welded connection or a pressure connection. 7. The power electronics arrangement, according to claim 6 , wherein: the thickness (D 5 ) of the first flat conductor connection is greater than the thickness (D 1 ) of the first flat conductor connection element; the thickness (D 6 ) of the second flat conductor connection is greater than the thickness (D 2 ) of the second flat conductor connection element; and the thickness (D 7 ) of the third flat conductor connection is greater than the thickness (D 3 ) of the third flat conductor connection element.

Assignees

Inventors

Classifications

  • Package configurations · CPC title

  • Shapes or dispositions of interconnections · CPC title

  • H10W90/701Primary

    characterised by the relative positions of pads or connectors relative to package parts · CPC title

  • Welded connections (H01R4/021 - H01R4/028 take precedence) · CPC title

  • H02M7/003Primary

    Constructional details, e.g. physical layout, assembly, wiring or busbar connections · CPC title

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What does patent US12368385B2 cover?
A power semiconductor module has a substrate that has an electrically non-conductive insulating layer and a first metal layer on the insulating layer and forms conductor tracks, with power semiconductor components arranged on the first metal layer and electrically connected to the first metal layer and having a DC voltage connection device that has a first, second and third flat conductor conne…
Who is the assignee on this patent?
Semikron Elektronik Gmbh & Co Kg
What technology area does this patent fall under?
Primary CPC classification H10W90/701. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 22 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).