Non-isolated resonant gate drive circuit

Patent metadata

Field	Value
Publication number	US-12368371-B2
Application number	US-202418850589-A
Country	US
Kind code	B2
Filing date	Mar 20, 2024
Priority date	Nov 30, 2023
Publication date	Jul 22, 2025
Grant date	Jul 22, 2025

Abstract

A non-isolated resonant gate drive circuit includes a PMOS drive network, an NMOS clamping circuit and an inductor. The PMOS drive network and the NMOS clamping circuit are connected in parallel to two terminals of the inductor. Input signals of the PMOS drive network are provided by a function generator connected to a drive chip, drive signals are output via an output port v gsr1 and an output port v gsr2 after the input signals are processed by the PMOS drive network, the NMOS clamping circuit and the inductor, the NMOS clamping circuit is used for controlling the state of the output port v gsr1 and the output port v gsr2 to change, and the inductor forms LC resonance together with a gate capacitor C gsr1 and a gate capacitor C gsr2 in the NMOS clamping circuit to recover energy in a process of turning off the drive circuit.

First claim

What is claimed is:

1. A non-isolated resonant gate drive circuit, comprising a P-channel metal oxide semiconductor (PMOS) drive network, an N-channel metal oxide semiconductor (NMOS) clamping circuit and an inductor, the PMOS drive network and the NMOS clamping circuit being connected in parallel to two terminals of the inductor;
wherein input signals of the PMOS drive network are provided by a function generator connected to a drive chip, drive signals are output via an output port v gsr1 and an output port v gsr2 after the input signals are processed by the PMOS drive network, the NMOS clamping circuit and the inductor, the NMOS clamping circuit is configured for controlling a state of the output port v gsr1 and the output port v gsr2 to change, the inductor forms LC resonance together with a capacitor C gsr1 and a capacitor C gsr2 in the NMOS clamping circuit to recover energy in a process of turning off the drive circuit, and the recovered energy is used in a process of turning on the drive circuit;
wherein the output port v gsr1 is connected to one terminal of the inductor and a drain of a first PMOS transistor, and the output port v gsr2 is connected to the other terminal of the inductor and a drain of a second PMOS transistor.

2. The non-isolated resonant gate drive circuit according to claim 1 , wherein the PMOS drive network comprises the first PMOS transistor and the second PMOS transistor, a source of the first PMOS transistor and a source of the second PMOS transistor are both connected to a power supply Vcc, a gate of the first PMOS transistor is connected to a pulse width modulation (PWM) 1 output port of the drive chip connected to the function generator, the drain of the first PMOS transistor is connected to one terminal of the inductor, a gate of the second PMOS transistor is connected to a PWM 2 output port of the drive chip connected to the function generator, and the drain of the second PMOS transistor is connected to the other terminal of the inductor.

3. The non-isolated resonant gate drive circuit according to claim 1 , wherein the NMOS clamping circuit comprises a first NMOS transistor, a second NMOS transistor, the capacitor C gsr1 and the capacitor C gsr2 ,
a gate of the first NMOS transistor is connected to a drain of the second NMOS transistor, the other terminal of the inductor, the output port v gsr2 , the drain of the second PMOS transistor and one terminal of the capacitor C gsr2 ,
a drain of the first NMOS transistor is connected to a gate of the second NMOS transistor, one terminal of the inductor, the output port v gsr1 , the drain of the first PMOS transistor and one terminal of the capacitor C gsr1 ,
a source of the first NMOS transistor is connected to the other terminal of the capacitor C gsr1 and ground (GND),
the gate of the second NMOS transistor is connected to one terminal of the inductor, the output port v gsr1 , the drain of the first PMOS transistor and the capacitor C gsr1 , the drain of the second NMOS transistor is connected to the other terminal of the inductor, the output port v gsr2 , the drain of the second PMOS transistor and one terminal of the capacitor C gsr2 ,
a source of the second NMOS transistor is connected to the other terminal of the capacitor C gsr2 and GND,
one terminal of the capacitor C gsr1 is connected to one terminal of the inductor, the output port v gsr1 and the drain of the first PMOS transistor, and
one terminal of the capacitor C gsr2 is connected to the other terminal of the inductor, the output port v gsr2 and the drain of the second PMOS transistor.

Assignees

• Univ Southeast

Inventors

• Qian Qinsong
• Zhou Ziyan
• Luo Qiang
• Liu Qi
• Ding Song
• Sun Weifeng
• Shi Longxing

Classifications

• H02M1/0054

  Transistor switching losses (periodically suspending operation of switching converter in low power mode H02M1/0035) · CPC title

• H02M3/33573

  Full-bridge at primary side of an isolation transformer · CPC title

• H03K17/162 Primary

  without feedback from the output circuit to the control circuit · CPC title

• H02M3/33592

  having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer · CPC title

• H02M3/01

  Resonant DC/DC converters · CPC title