Fault protected signal splitter apparatus

Patent metadata

Field	Value
Publication number	US-12368223-B2
Application number	US-202418629483-A
Country	US
Kind code	B2
Filing date	Apr 8, 2024
Priority date	Sep 10, 2021
Publication date	Jul 22, 2025
Grant date	Jul 22, 2025

Abstract

A system is disclosed herein. The system includes a splitter board. The splitter board includes a microprocessor, a converter, and a bypass relay. The converter includes analog-to-digital circuitry and digital-to-analog circuitry. The bypass relay is configurable between a first state and a second state. In the first state, the bypass relay is configured to direct an input signal to the converter. The converter converts the input signal to a converted input signal and splits the converted input signal into a first portion and a second portion. The first portion is directed to the microprocessor. The second portion is directed to an output port of the splitter board for downstream processes. In the second state, the bypass relay is configured to cause the input signal to bypass the converter. The bypass relay directs the input signal to the output port of the splitter board for the downstream processes.

First claim

The invention claimed is:

1. A splitter board system comprising:
a microprocessor; and
a converter coupled with the microprocessor, the converter comprising analog-to-digital circuitry and digital-to-analog circuitry,
wherein the converter is configured to:
receive an input signal, wherein the input signal is in a first signal type, the first signal type being one of an analog signal or a digital signal;
generate a first duplicated instance of the input signal,
generate a second duplicated instance of the input signal,
convert at least one of the first duplicated instance of the input signal or the second duplicated instance of the input signal into a second signal type, the second signal type being one of an analog signal or a digital signal,
direct the first duplicated instance to an output port of the splitter board system for downstream processes, and
output the second duplicated instance to an external server device.

2. The splitter board system of claim 1 , wherein the first duplicated instance is converted to a digital signal and directed to the microprocessor prior to output via the output port.

3. The splitter board system of claim 2 , wherein the microprocessor applies calibration factors to the first duplicated instance and returns the first duplicated instance to the converter after the calibration factors are applied.

4. The splitter board system of claim 3 , wherein the converter is further configured to:
convert the first duplicated instance of the input signal back to the first signal type prior to output.

5. The splitter board system of claim 1 , further comprising:
a bypass coupled with the converter and the microprocessor, the bypass configurable between a first state and a second state.

6. The splitter board system of claim 5 , wherein, in the first state, the bypass directs the input signal to the converter.

7. The splitter board system of claim 5 , wherein, in the second state, the bypass directs the input signal towards the output port, bypassing the converter.

8. A splitter board system comprising:
a converter;
a bypass coupled to the converter, the bypass configurable between a first state and a second state; and
a microprocessor coupled with the converter and the bypass, the microprocessor configured to switch the bypass between the first state and the second state,
wherein, in the first state, the bypass directs a fault protected input signal to the converter, the fault protected input signal being in a first signal type, the first signal type being one of an analog signal or a digital signal, wherein the converter splits the fault protected input signal into a first portion and a second portion, converts at least one of the first portion or the second portion into a second signal type, the second signal type being one of an analog signal or a digital signal, and directs the first portion of the fault protected input signal to an output port of the splitter board system for downstream processes and outputs the second portion to an external server device, and
wherein, in the second state, the bypass causes the fault protected input signal to bypass the converter and directs the fault protected input signal to the output port of the splitter board system for the downstream processes.

9. The splitter board system of claim 8 , wherein the converter directs the first portion of the fault protected input signal to the microprocessor prior to output.

10. The splitter board system of claim 9 , wherein the microprocessor applies calibration factors to the second portion of the fault protected input signal and returns the second portion of the fault protected input signal to the converter after the calibration factors are applied.

11. The splitter board system of claim 10 , wherein the converter is further configured to:
convert the second portion of the fault protected input signal back to the first signal type.

12. The splitter board system of claim 8 , wherein the converter comprising:
a fault detection module configured to detect when at least one component of the splitter board system fails.

13. The splitter board system of claim 12 , wherein the microprocessor is configured to read the fault detection module to determine when the at least one component of the splitter board system fails.

14. The splitter board system of claim 12 , wherein responsive to determining that at least one component of the splitter board system fails, switching the bypass to the second state.

15. A method comprising:
receiving, by a converter of a signal splitter board, an input signal, wherein the input signal is in a first signal type, the first signal type being one of an analog signal or a digital signal;
generating, by the converter, a first duplicated instance of the input signal;
generating, by the converter, a second duplicated instance of the input signal;
converting, by the converter, at least one of the first duplicated instance of the input signal or the second duplicated instance of the input signal into a second signal type, the second signal type being one of an analog signal or a digital signal;
directing, by the converter, the first duplicated instance to an output port of the signal splitter board for downstream processes; and
outputting, by the converter, the digital signal to an external server device.

16. The method of claim 15 , wherein the first duplicated instance is converted to a digital signal and directed to a microprocessor of the signal splitter board prior to output via the output port.

17. The method of claim 16 , further comprising:
applying, by the microprocessor, calibration factors to the first duplicated instance; and
returning, by the microprocessor, the first duplicated instance to the converter after the calibration factors are applied.

18. The method of claim 17 , further comprising:
converting, by the converter, the first duplicated instance back to the first signal type.

19. The method of claim 15 , wherein the converter comprises a fault detection module.

20. The method of claim 19 , further comprising:
determining, by the fault detection module, that no component of the signal splitter board failed.

Assignees

• Nanotronics Imaging Inc

Inventors

• Putman John B
• Putman Matthew C
• Limoge Damas
• Moskie Michael
• Lee Joanna

Classifications

• H03M1/12

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H02H7/20

  for electronic equipment (for converters H02H7/10; for electric measuring instruments G01R1/36; for DC voltage or current semiconductor regulators G05F1/569; for amplifiers H03F1/52; for electronic switching circuits H03K17/08) · CPC title

• H03M1/1009 Primary

  Calibration · CPC title

• G01R31/3177

  Testing of logic operation, e.g. by logic analysers · CPC title

• G06F13/4068

  Electrical coupling · CPC title