Manufacturing method of semiconductor structure comprising a gap and semiconductor structure comprising a gap

Patent metadata

Field	Value
Publication number	US-12368074-B2
Application number	US-202217648952-A
Country	US
Kind code	B2
Filing date	Jan 26, 2022
Priority date	Jan 4, 2021
Publication date	Jul 22, 2025
Grant date	Jul 22, 2025

Abstract

Embodiments of the present application provide a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method includes: providing a base with an electrical contact layer therein; forming an insulating layer on the base, the insulating layer having a through hole penetrating the insulating layer, and the through hole exposing a surface of the electrical contact layer; forming a sidewall layer on a sidewall of the through hole; forming a first isolation layer, the first isolation layer covering a surface of the sidewall layer and an exposed surface of the insulating layer; removing the sidewall layer to form a gap between the first isolation layer and the insulating layer; and forming a conducting layer filling the through hole, the conducting layer being electrically connected to the electrical contact layer.

First claim

What is claimed is:

1. A manufacturing method of a semiconductor structure, comprising:
providing a base with an electrical contact layer therein;
forming an insulating layer on the base, the insulating layer having a through hole penetrating the insulating layer, and the through hole exposing a surface of the electrical contact layer;
forming a sidewall layer on a sidewall of the through hole;
forming a first isolation layer, the first isolation layer covering a surface of the sidewall layer and an exposed surface of the insulating layer;
removing the sidewall layer to form a gap between the first isolation layer and the insulating layer;
forming a second isolation layer on a surface of the first isolation layer, a density of the second isolation layer being greater than that of the first isolation layer, wherein the second isolation layer consists of silicon dioxide or silicon nitride; and
forming a conducting layer filling the through hole, the conducting layer being electrically connected to the electrical contact layer.

2. The manufacturing method of a semiconductor structure according to claim 1 , wherein a method for removing the sidewall layer comprises:
providing a plasma source, causing an ion beam generated by the plasma source to react with the sidewall layer after passing through the first isolation layer and form reaction byproducts, and discharging at least part of the reaction byproducts through the first isolation layer.

3. The manufacturing method of a semiconductor structure according to claim 2 , wherein the process step of removing the sidewall layer comprises: generating the ion beam based on an oxygen plasma source, wherein a flow rate of oxygen is within a range of 100 sccm to 600 sccm, and a radio frequency power is within a range of 500 W to 1000 W.

4. The manufacturing method of a semiconductor structure according to claim 1 , wherein the sidewall layer is made of amorphous carbon, hydrocarbon or a polymer.

5. The manufacturing method of a semiconductor structure according to claim 1 , wherein a top surface of the sidewall layer is lower than a top surface of the insulating layer, and the step of forming the sidewall layer comprises: forming an initial sidewall layer on a surface of the insulating layer and a bottom of the through hole; and removing the initial sidewall layer located at the bottom of the through hole and the top surface of the insulating layer, and further removing a part of the initial sidewall layer located on the sidewall of the through hole, the remaining initial sidewall layer serving as the sidewall layer.

6. The manufacturing method of a semiconductor structure according to claim 5 , wherein in a direction perpendicular to a surface of the base, a ratio of a height of the sidewall layer to a height of the insulating layer is greater than or equal to 0.3.

7. The manufacturing method of a semiconductor structure according to claim 1 , subsequent to the formation of the conducting layer, further comprising a step of planarization to remove part of the conducting layer, part of the insulating layer, part of the first isolation layer and part of the second isolation layer which are higher than the gap.

8. The manufacturing method of a semiconductor structure according to claim 1 , wherein a method for forming the first isolation layer comprises: a low-temperature atomic layer deposition process.

9. The manufacturing method of a semiconductor structure according to claim 1 , wherein the first isolation layer is made of silicon dioxide or silicon-oxyhydrocarbon.

10. The manufacturing method of a semiconductor structure according to claim 1 , prior to the step of forming the conducting layer filling the through hole, further comprising a step of removing the first isolation layer and the second isolation layer located at a bottom of the through hole and a top surface of the insulating layer; and depositing a barrier layer covering the sidewall of the through hole.

Assignees

• Changxin Memory Tech Inc
• Changxi Memory Tech Inc

Inventors

• Li Ting
• Chou Hou-Hong

Classifications

• H10P50/287 Primary

  by chemical means · CPC title

• H10P50/285

  of materials not containing Si, e.g. PZT or Al2O3 · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6922

  the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC · CPC title

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title