Display substrate and display apparatus

Patent metadata

Field	Value
Publication number	US-12367823-B2
Application number	US-202218031347-A
Country	US
Kind code	B2
Filing date	Jun 2, 2022
Priority date	Jun 2, 2022
Publication date	Jul 22, 2025
Grant date	Jul 22, 2025

Abstract

Disclosed are a display substrate and a display apparatus, the display substrate includes a display region and a non-display region, the display substrate includes a base substrate and a circuit structure layer disposed on the base substrate, the circuit structure layer includes multiple pixel circuits arranged in an array and located in the display region and multiple drive circuits located in the non-display region. At least one pixel circuit includes multiple transistors and the multiple drive circuits are configured to provide drive signals to the multiple transistors; the circuit structure layer further includes: a high-level power supply line and a low-level power supply line located in the non-display region, at least one drive circuit is electrically connected with the high-level power supply line and the low-level power supply line respectively, and the high-level power supply line and the low-level power supply line extend along a first direction.

First claim

The invention claimed is:

1. A display substrate, comprising a display region and a non-display region, wherein;
the display substrate comprises: a base substrate and a circuit structure layer disposed on the base substrate, the circuit structure layer comprises: a plurality of pixel circuits arranged in an array and located in the display region and a plurality of drive circuits located in the non-display region; at least one pixel circuit comprises a plurality of transistors, the plurality of drive circuits are configured to provide drive signals to the plurality of transistors;
the circuit structure layer further comprises: a high-level power supply line and a low-level power supply line located in the non-display region, at least one drive circuit is electrically connected with the high-level power supply line and the low-level power supply line respectively, and the high-level power supply line and the low-level power supply line extend along a first direction;
high-level power supply lines connected with at least two drive circuits are a same power supply line and/or low-level power supply lines connected with at least two drive circuits are a same power supply line;
the circuit structure layer comprises: a semiconductor layer, a first insulation layer, a first conductive layer, a second insulation layer, a second conductive layer, a third insulation layer, a third conductive layer, a fourth insulation layer, and a fourth conductive layer that are sequentially stacked on the base substrate;
the high-level power supply line and the low-level power supply line are located in the third conductive layer and/or the fourth conductive layer;
the plurality of transistors comprise: a writing transistor, a compensation transistor, and a light emitting transistor, and the plurality of drive circuits comprise: a light emitting drive circuit and a control drive circuit; the light emitting drive circuit is configured to provide a drive signal to the light emitting transistor, and the control drive circuit is configured to provide a drive signal to the writing transistor and/or the compensation transistor; and
a high-level power supply line connected with the light emitting drive circuit and a high-level power supply line connected with the control drive circuit are a same power supply line and/or a low-level power supply line connected with the light emitting drive circuit and a low-level power supply line connected with the control drive circuit are a same power supply line.

2. The display substrate according to claim 1 , wherein the display region comprises: a first side and a second side disposed opposite to each other, and at least one drive circuit is located on the first side and/or the second side of the display region;
the plurality of drive circuits extend along a second direction, and the first direction intersects with the second direction.

3. The display substrate according to claim 1 , wherein the circuit structure layer further comprises: a fifth insulation layer and a fifth conductive layer;
the fifth insulation layer and the fifth conductive layer are located between the second conductive layer and the third insulation layer, and the fifth insulation layer is located on a side of the fifth conductive layer close to the base substrate.

4. The display substrate according to claim 1 , wherein when the high-level power supply line connected with the light emitting drive circuit and the high-level power supply line connected with the control drive circuit are the same power supply line, an orthographic projection of the high-level power supply line on the base substrate is at least partially overlapped with an orthographic projection of the light emitting drive circuit or the control drive circuit on the base substrate, or is located between the light emitting drive circuit and the control drive circuit.

5. The display substrate according to claim 1 , wherein when the low-level power supply line connected with the light emitting drive circuit and the low-level power supply line connected with the control drive circuit are the same power supply line, an orthographic projection of the low-level power supply line on the base substrate is at least partially overlapped with an orthographic projection of the light emitting drive circuit or the control drive circuit on the base substrate, or is located between the light emitting drive circuit and the control drive circuit.

6. The display substrate according to claim 1 , wherein the light emitting drive circuit is located on a side of the control drive circuit away from the display region;
the circuit structure layer further comprises: a light emitting initial signal line, a plurality of light emitting clock signal lines, a control initial signal line, and a plurality of control clock signal lines which are located in the non-display region and extending along the first direction; the light emitting drive circuit is electrically connected with the light emitting initial signal line and the plurality of light emitting clock signal lines respectively, and the control drive circuit is electrically connected with the control initial signal line and the plurality of control clock signal lines respectively;
the light emitting initial signal line and the plurality of light emitting clock signal lines are located on a side of the control initial signal line and the plurality of control clock signal lines away from the display region, and the light emitting initial signal line is located on a side of the plurality of light emitting clock signal lines close to or away from the display region; and
the control initial signal line is located on a side of the plurality of control clock signal lines close to the display region or away from the display region.

7. The display substrate according to claim 6 , wherein the light emitting drive circuit comprises a plurality of light emitting transistors and a plurality of light emitting capacitors, and the control drive circuit comprises a plurality of control transistors and a plurality of control capacitors;
the first conductive layer comprises: gate electrodes of the plurality of light emitting transistors, gate electrodes of the plurality of control transistors, first electrode plates of the plurality of light emitting capacitors, and first electrode plates of the plurality of control capacitors;
the second conductive layer comprises: second electrode plates of the plurality of light emitting capacitors and second electrode plates of the plurality of control capacitors;
the third conductive layer comprises: source-drain electrodes of the plurality of light emitting transistors and source-drain electrodes of the plurality of control transistors;
the fourth conductive layer comprises a light emitting initial signal line, at least one light emitting clock signal line, a control initial signal line, and at least one control clock signal line.

8. The display substrate according to claim 1 , wherein the plurality of transistors comprise: a writing transistor, a first reset transistor, a compensation transistor, and a light emitting transistor, transistor types of the first reset transistor and the compensation transistor are different from transistor types of the writing transistor and the light emitting transistor, the plurality of drive circuits comprise: a light emitting drive circuit, a scan drive circuit, and a control drive circuit; the light emitting drive circuit is configured to provide a drive signal to the light emitting transistor, the control drive circuit is configured to provide a drive signal to the writing transistor, and the scan drive circuit is configured to provide a drive signal to the first reset transistor and/or the compensation transistor;
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Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Li Yujing
• Hu Ming
• Dong Xiangdan
• Fan Cong
• Wang Rong
• Zhang Zhenhua
• Tong Kemeng

Classifications

• G09G2330/023

  using energy recovery or conservation · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G3/3266

  Details of drivers for scan electrodes · CPC title