Pixel circuit, driving method therefor and display apparatus

Patent metadata

Field	Value
Publication number	US-12367807-B2
Application number	US-202218027494-A
Country	US
Kind code	B2
Filing date	Jun 22, 2022
Priority date	Jun 22, 2022
Publication date	Jul 22, 2025
Grant date	Jul 22, 2025

Abstract

Embodiments of the present disclosure provide a pixel circuit, a driving method therefor and a display apparatus. The pixel circuit includes: an input circuit, configured to input data signals loaded to a first data signal terminal into corresponding input nodes in response to signals loaded to 2 N −1 first scanning signal terminals; a control circuit, configured to control signals of 2 N control nodes respectively in response to signals of at least two input nodes in the 2 N −1 input nodes; an output circuit, configured to provide a signal of an m th selection control signal terminal in 2 N selection control signal terminals to an output node in response to a signal of an m th control node in the 2 N control nodes; and a light-emitting drive circuit, configured to drive a to-be-driven device to work in response to a signal of the output node.

First claim

What is claimed is:

1. A pixel circuit, comprising:
an input circuit, coupled with a first data signal terminal, 2 N −1 first scanning signal terminals and 2 N −1 input nodes respectively, wherein the 2 N −1 first scanning signal terminals are in one-to-one correspondence with the 2 N −1 input nodes, the input circuit is configured to input data signals loaded to the first data signal terminal into the corresponding input nodes in response to signals loaded to the 2 N −1 first scanning signal terminals, and N is an integer greater than 1;
a control circuit, coupled with the 2 N −1 input nodes respectively, wherein the control circuit is configured to control signals of 2 N control nodes respectively in response to signals of at least two input nodes in the 2 N −1 input nodes;
an output circuit, coupled with the 2 N control nodes, 2 N selection control signal terminals and an output node respectively, wherein the 2 N control nodes are in one-to-one correspondence with the 2 N selection control signal terminals, the output circuit is configured to provide a signal of an m th selection control signal terminal in the 2 N selection control signal terminals to the output node in response to a signal of an m th control node in the 2 N control nodes, 1≤m≤2N, and m is an integer; and
a light-emitting drive circuit, coupled with the output node and a to-be-driven device respectively, wherein the light-emitting drive circuit is configured to drive the to-be-driven device to work in response to a signal of the output node;
wherein the control circuit comprises: 2 N −1 control sub-circuits, and input terminals of the 2 N −1 control sub-circuits are coupled with the 2 N −1 input nodes in a one-to-one correspondence;
the 2 N −1 control sub-circuits are defined as a first-stage control sub-circuit to an N th -stage control sub-circuit; wherein each N th -stage control sub-circuit is in one-to-one correspondence with two control nodes in the 2 N control nodes, an input terminal of the N th -stage control sub-circuit is coupled with one control node in the corresponding two control nodes, and an output terminal of the N th -stage control sub-circuit is coupled with the other control node in the corresponding two control nodes;
each (q−1) th -stage control sub-circuit corresponds to two q th -stage control sub-circuits, a control terminal of one q th -stage control sub-circuit in the two q th -stage control sub-circuits is coupled with an output terminal of the corresponding (q−1) th -stage control sub-circuit, and a control terminal of the other q th -stage control sub-circuit in the two q th -stage control sub-circuits is coupled with an input terminal of the corresponding (q−1) th -stage control sub-circuit;
and the q th -stage control sub-circuits are configured to provide signals of input terminals to output terminals thereof in response to signals loaded to the control terminals thereof; and
2≤q≤N, and q is an integer.

2. The pixel circuit according to claim 1 , wherein the input circuit comprises: 2 N −1 input sub-circuits, wherein a k th input sub-circuit in the 2 N −1 input sub-circuits is coupled with a k th first scanning signal terminal in the 2 N −1 first scanning signal terminals and a k th input node in the 2 N −1 input nodes respectively;
the k th input sub-circuit is configured to input a data signal loaded to the first data signal terminal into the k th input node in response to a signal loaded to the k th first scanning signal terminal; and 1≤k≤2 N −1, and k is an integer.

3. The pixel circuit according to claim 2 , wherein the k th input sub-circuit comprises a k th first transistor; and
a control terminal of the k th first transistor is coupled with the k th first scanning signal terminal, a first terminal of the k th first transistor is coupled with the first data signal terminal, and a second terminal of the k th first transistor is coupled with the k th input node.

4. The pixel circuit according to claim 1 , wherein the first-stage control sub-circuit comprises a first latch; and
an input terminal of the first latch serves as an input terminal of the first-stage control sub-circuit, and an output terminal of the first latch serves as an output terminal of the first-stage control sub-circuit.

5. The pixel circuit according to claim 4 , wherein the first latch comprises: a first phase inverter and a second phase inverter;
an input terminal of the first phase inverter serves as the input terminal of the first latch, and an output terminal of the first phase inverter serves as the output terminal of the first latch; and
an input terminal of the second phase inverter is coupled with the output terminal of the first phase inverter, and an output terminal of the second phase inverter is coupled with the input terminal of the first phase inverter.

6. The pixel circuit according to claim 1 , wherein the q th -stage control sub-circuit comprises: a second latch; and
a control terminal of the second latch serves as a control terminal of the q th -stage control sub-circuit, an input terminal of the second latch serves as an input terminal of the q th -stage control sub-circuit, and an output terminal of the second latch serves as an output terminal of the q th -stage control sub-circuit.

7. The pixel circuit according to claim 6 , wherein the second latch comprises: a first tri-state gate and a second tri-state gate;
a control terminal of the first tri-state gate serves as the control terminal of the second latch, an input terminal of the first tri-state gate serves as the input terminal of the second latch, and an output terminal of the first tri-state gate serves as the output terminal of the second latch; and
a control terminal of the second tri-state gate is coupled with the control terminal of the first tri-state gate, an input terminal of the second tri-state gate is coupled with the output terminal of the first tri-state gate, and an output terminal of the second tri-state gate is coupled with the input terminal of the first tri-state gate.

8. The pixel circuit according to claim 1 , wherein the output circuit comprises: 2 N output sub-circuits; an m th output sub-circuit in the 2 N output sub-circuits is coupled with the m th control node, the m th selection control signal terminal and the output node; and
the m th output sub-circuit is configured to provide the signal of the m th selection control signal terminal to the output node in response to the signal of the m th control node.

9. The pixel circuit according to claim 8 , wherein the m th output sub-circuit comprises an m th second transistor;
a control terminal of the m th second transistor is coupled with the m th control node, a first terminal of the m th second transistor is coupled with the m th selection control signal terminal, and a second terminal of the m th second transistor is coupled with the output node.

10. The pixel circuit according to claim 1 , wherein the light-emitting drive circuit comprises: a light-emitting control sub-circuit;
the light-emitting control sub-circuit is coupled with the output node, a light-emitting control signal terminal and the to-be-driven device respectively; and the light-emitting control sub-circuit is configured to drive the to-be-driven device to work in response to signals of the light-emitting control signal terminal and the output node.

11. The pixel circuit according to claim 10 , wherein the light-emitting control sub-circuit comprises a third transistor; and a control terminal of the third transistor is coupled with the light-emitting control signal terminal, a first terminal of the third transistor is coupled with the output node, a

Assignees

• Beijing Boe Display Tech Co
• Boe Technology Group Co Ltd

Inventors

• Cong Ning
• Xuan Minghua
• Zhang Can
• Wang Can
• Niu Jinfei
• Zhang Jingjing
• Han Seungwoo

Classifications

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G3/3233

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• G09G3/32 Primary

  semiconductive, e.g. using light-emitting diodes [LED] · CPC title