Performing memory access operations with a logical-to-physical mapping table with reduced size

Patent metadata

Field	Value
Publication number	US-12367156-B2
Application number	US-202418582926-A
Country	US
Kind code	B2
Filing date	Feb 21, 2024
Priority date	Dec 29, 2021
Publication date	Jul 22, 2025
Grant date	Jul 22, 2025

Abstract

A logical-to-physical (L2P) data structure comprising a plurality of L2P table entries is maintained on the volatile memory device. Each L2P table entry comprises a block number and a page table index corresponding to the non-volatile memory device. A plurality of physical-to-logical (P2L) data structures each comprising a plurality of P2L table entries is maintained on the volatile memory device. Each of the plurality of P2L data structures corresponds to a portion of the L2P data structure.

First claim

What is claimed is:

1. A system comprising:
a volatile memory device;
a non-volatile memory device; and
a processing device, operatively coupled with the volatile memory device and the non-volatile memory device, to perform operations comprising:
responsive to receiving a request to perform a memory access operation on a logical address of the non-volatile memory device, identifying a physical-to-logical (P2L) data structure based on an entry of a logical-to-physical (L2P) data structure indexed by the logical address comprising a block number and page table index associated with the P2L data structure of a plurality of P2L data structures;
searching the P2L data structure for an entry matching the logical address to translate the logical address to a physical address; and
performing the memory access operation using the physical address.

2. The system of claim 1 , wherein the L2P data structure and the plurality of P2L data structure are maintained on the volatile memory device.

3. The system of claim 1 , wherein translating the logical address to the physical address includes composing the physical address based on a location of the matching entry in the P2L data structure.

4. The system of claim 1 , wherein each entry of the P2L data structure records logical translation unit information for each physical address covered by the P2L data structure.

5. The system of claim 4 , wherein each P2L data structure covers one or more pages of a block across logical units with an identical page index.

6. The system of claim 1 , wherein searching the P2L data structure for the entry matching the logical address to translate the logical address to a physical address includes traversing each entry of the P2L data structure in reverse order starting with a last entry of the P2L data structure to a first entry of the P2L data structure until an entry of the P2L data structure matches the logical address.

7. The system of claim 1 , wherein searching the P2L data structure for the entry matching the logical address to translate the logical address to a physical address includes partitioning the P2L data structure into a plurality of consecutive portions that are indicative of their ordering in the P2L data structure and traversing, in parallel, each entry of the plurality of consecutive portions of the P2L data structure in reverse order starting with a last entry to a first entry until one of: an entry of the P2L data structure in a respective portion of the P2L data structure matches the logical address or the first entry in the respective portion of the plurality of consecutive portions of the P2L data structure is reached without matching the logical address.

8. A method comprising:
responsive to receiving a request to perform a memory access operation on a logical address of a non-volatile memory device, identifying a physical-to-logical (P2L) data structure based on an entry of a logical-to-physical (L2P) data structure indexed by the logical address comprising a block number and page table index associated with the P2L data structure of a plurality of P2L data structures;
searching the P2L data structure for an entry matching the logical address to translate the logical address to a physical address; and
performing the memory access operation using the physical address.

9. The method of claim 8 , wherein the L2P data structure and the plurality of P2L data structure are maintained on a volatile memory device.

10. The method of claim 8 , wherein translating the logical address to the physical address includes composing the physical address based on a location of the matching entry in the P2L data structure.

11. The method of claim 8 , wherein each entry of the P2L data structure records logical translation unit information for each physical address covered by the P2L data structure.

12. The method of claim 11 , wherein each P2L data structure covers one or more pages of a block across logical units with an identical page index.

13. The method of claim 8 , wherein searching the P2L data structure for the entry matching the logical address to translate the logical address to a physical address includes traversing each entry of the P2L data structure in reverse order starting with a last entry of the P2L data structure to a first entry of the P2L data structure until an entry of the P2L data structure matches the logical address.

14. The method of claim 8 , wherein searching the P2L data structure for the entry matching the logical address to translate the logical address to a physical address includes partitioning the P2L data structure into a plurality of consecutive portions that are indicative of their ordering in the P2L data structure and traversing, in parallel, each entry of the plurality of consecutive portions of the P2L data structure in reverse order starting with a last entry to a first entry until one of: an entry of the P2L data structure in a respective portion of the P2L data structure matches the logical address or the first entry in the respective portion of the plurality of consecutive portions of the P2L data structure is reached without matching the logical address.

15. A non-transitory computer-readable medium comprising instructions that, responsive to execution by a processing device, cause the processing device to perform operations comprising:
responsive to receiving a request to perform a memory access operation on a logical address of a non-volatile memory device, identifying a physical-to-logical (P2L) data structure based on an entry of a logical-to-physical (L2P) data structure indexed by the logical address comprising a block number and page table index associated with the P2L data structure of a plurality of P2L data structures;
searching the P2L data structure for an entry matching the logical address to translate the logical address to a physical address; and
performing the memory access operation using the physical address.

16. The non-transitory computer-readable medium of claim 15 , wherein the L2P data structure and the plurality of P2L data structure are maintained on a volatile memory device.

17. The non-transitory computer-readable medium of claim 15 , wherein translating the logical address to the physical address includes composing the physical address based on a location of the matching entry in the P2L data structure.

18. The non-transitory computer-readable medium of claim 15 , wherein each entry of the P2L data structure records logical translation unit information for each physical address covered by the P2L data structure.

19. The non-transitory computer-readable medium of claim 18 , wherein each P2L data structure covers one or more pages of a block across logical units with an identical page index.

20. The non-transitory computer-readable medium of claim 15 , wherein searching the P2L data structure for the entry matching the logical address to translate the logical address to a physical address includes traversing each entry of the P2L data structure in reverse order starting with a last entry of the P2L data structure to a first entry of the P2L data structure until an entry of the P2L data structure matches the logical address.

Assignees

• Micron Technology Inc

Inventors

• Wei Meng

Classifications

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F12/0891

  using clearing, invalidating or resetting means · CPC title

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title

• G06F12/0238

  Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory · CPC title

• G06F12/1009 Primary

  using page tables, e.g. page table structures · CPC title