Fault detection circuit

Patent metadata

Field	Value
Publication number	US-12366607-B2
Application number	US-202318477128-A
Country	US
Kind code	B2
Filing date	Sep 28, 2023
Priority date	Sep 28, 2023
Publication date	Jul 22, 2025
Grant date	Jul 22, 2025

Abstract

Fault detection circuits and methods. An example of a fault detection circuit includes a comparator configured to compare a voltage at a voltage terminal with a reference voltage, a digital logic circuit coupled to a test terminal and configured to receive, responsive to the voltage at the voltage terminal being less than the reference voltage as indicated by the comparator, a test signal, the digital logic circuit including at least one digital logic gate, and an edge detection circuit configured to (a) monitor a signal produced at an output of the at least one digital logic gate, and (b) based on the signal failing to transgress a threshold within a time period, providing a fault signal indicating detection of a fault at the test terminal.

First claim

What is claimed is:

1. A circuit comprising:
a first logic gate having a first input coupled to a first terminal;
a second logic gate having a first input coupled to a second terminal, an output of the second logic gate coupled to a second input of the first logic gate;
a first logic circuit;
a voltage comparator having first and second comparator inputs and a comparator output, the first comparator input coupled to a voltage terminal, the second comparator input coupled to a reference voltage terminal, and the comparator output coupled to an input of the first logic circuit;
a delay device having an input coupled to the second terminal, and an output of the delay device is coupled to a second input of the second logic gate; and
a second logic circuit having a first input coupled to an output of the first logic gate, a second input coupled to an output of the first logic circuit, and having at least one fault detection output.

2. The circuit of claim 1 , wherein the second logic circuit includes a third logic circuit having a clock terminal coupled to the output of the first logic gate and an input coupled to an output of the first logic circuit.

3. The circuit of claim 2 , wherein the second logic circuit further comprises:
a third logic gate having a first input coupled to the output of the second logic gate, a second input coupled to a fault terminal of the third logic circuit, and a third input coupled to the first terminal; and
a fourth logic circuit having a clock terminal coupled to an output of the third logic gate and an input coupled to the output of the first logic circuit.

4. The circuit of claim 3 , wherein the first, third, and fourth logic circuits are digital latches.

5. The circuit of claim 1 , wherein the first and second logic gates are AND gates.

6. The circuit of claim 5 , further comprising:
an inverter coupled between the delay device and the second input of the second logic gate.

7. The circuit of claim 1 , wherein the voltage terminal is coupled to the first terminal;
wherein the voltage comparator is configurable to compare a test voltage at the first terminal to a reference voltage at the reference voltage terminal; and
wherein, based on the test voltage being less than the reference voltage, the second logic circuit is configurable to monitor a first test signal produced at the output of the first logic gate in response to a second test signal applied to the second terminal, the second logic circuit being further configurable to produce, at the at least one fault detection output, a fault signal based on a failure of the first test signal to transgress a threshold value within a time period, the fault signal being indicative of a fault condition at the first terminal.

8. The circuit of claim 1 , wherein the voltage terminal is coupled to a regulator output voltage feedback;
wherein the voltage comparator is configurable to compare a test voltage at the voltage terminal to a reference voltage at the reference voltage terminal; and
wherein, based on the test voltage being less than the reference voltage, the second logic circuit is configurable to monitor a first test signal produced at the output of the first logic gate in response to a second test signal applied to the second terminal, the second logic circuit being further configurable to produce, at the at least one fault detection output, a fault signal based on a failure of the first test signal to transgress a threshold value within a time period, the fault signal being indicative of a fault condition at the first terminal.

9. The circuit of claim 1 , wherein the voltage terminal is coupled to one of: (i) a switching voltage terminal to receive a switching voltage of a power converter; or (ii) an output voltage feedback terminal to receive a feedback voltage representative of an output voltage of the power converter;
wherein the voltage comparator is configurable to compare a test voltage at the voltage terminal to a reference voltage at the reference voltage terminal; and
wherein, based on a comparison of the test voltage to the reference voltage, the second logic circuit is configurable to monitor a first test signal produced at the output of the first logic gate in response to a second test signal applied to the second terminal, the second logic circuit being further configurable to produce, at the at least one fault detection output, a fault signal based on a failure of the first test signal to transgress a threshold value within a time period, the fault signal being indicative of a fault condition at the first terminal.

10. The circuit of claim 9 , wherein the fault condition comprises at least one of an absence of a capacitor coupled to the first terminal, an absence of an inductor coupled to the first terminal, or a short circuit condition at the first terminal.

11. The circuit of claim 1 , further comprising a transistor coupled between the first terminal and the first input of the first logic gate.

12. A circuit comprising:
a voltage comparator having first and second comparator inputs and a comparator output, the first comparator input coupled to a reference voltage terminal;
a first logic circuitry coupled to a first terminal, a second terminal, and the comparator output; and
a delay device coupled between the second terminal and the first logic circuitry, the delay device configurable to produce a delayed copy of a test signal applied at the second terminal;
wherein the first logic circuitry is configurable to produce a monitor signal based on a combination of the test signal, the delayed copy of the test signal, and a test voltage at the first terminal, and to produce a fault signal indicative of the fault based on a failure of the monitor signal to transgress a threshold value within a time period.

13. The circuit of claim 12 , wherein the first logic circuitry comprises:
a first logic gate having a first input coupled to the first terminal;
a second logic gate having a first input coupled to the second terminal, a second input coupled to the delay device, and an output coupled to a second input of the first logic gate; and
a second logic circuit having an input coupled to the comparator output.

14. The circuit of claim 13 , wherein the first logic circuitry further comprises a third logic circuit having a clock terminal coupled to an output of the first logic gate and an input coupled to an output of the second logic circuit.

15. The circuit of claim 14 , wherein the first logic circuitry further comprises:
a third logic gate having a first input coupled to the output of the second logic gate, a second input coupled to a fault terminal of the third logic circuit, and a third input coupled to the first terminal; and
a fourth logic circuit having a clock terminal coupled to an output of the third logic gate and an input coupled to the output of the second logic circuit.

16. The circuit of claim 13 , wherein the first and second logic gates are AND gates.

17. The circuit of claim 16 , wherein a switch is coupled between an input supply voltage and first terminal; and wherein the fault comprises at least one of absence of a capacitor coupled between the switch and the first terminal, absence of an inductor coupled between the first terminal and a regulator output, or a short circuit condition at the first terminal.

18. The circuit of claim 12 , wherein a switch is coupled between an input supply voltage and first terminal; wherein the second comparator input is coupled to the first terminal; wherein the voltage comparator is configurabl

Assignees

• Texas Instruments Inc

Inventors

• Jing Weibing

Classifications

• G01R31/31932

  Comparators · CPC title

• G01R31/31712

  Input or output aspects · CPC title

• G01R19/175

  Indicating the instants of passage of current or voltage through a given value, e.g. passage through zero · CPC title

• G01R19/16585

  for individual pulses, ripple or noise and other applications where timing or duration is of importance (G01R19/16519, G01R19/16538 and G01R19/16595 take precedence; for pulse duration and rise time, see G01R29/02 and subgroups) · CPC title

• G01R19/16571

  comparing AC or DC current with one threshold, e.g. load current, over-current, surge current or fault current (G01R19/16514, G01R19/16519, G01R19/16528, G01R19/16533, G01R19/1659 take precedence; measuring currents by using elements sensitive to the magnetic field generated G01R15/14; measuring earth resistance G01R27/18; testing for leakage or short circuits in electrical apparatus G01R31/52) · CPC title