Area, cost, and time-effective scan coverage improvement

Patent metadata

Field	Value
Publication number	US-12366605-B2
Application number	US-202318100975-A
Country	US
Kind code	B2
Filing date	Jan 24, 2023
Priority date	Jan 24, 2023
Publication date	Jul 22, 2025
Grant date	Jul 22, 2025

Abstract

According to an embodiment, a digital circuit includes an OR gate and a flip-flop. The OR gate includes a first input and a second input. The first input of the OR gate is coupled to a control signal, and the second input of the OR gate is coupled to an uncovered functional combination logic of the digital circuit. The first input of the OR gate is configured to be pulled low by the control signal in response to setting the digital circuit in a configuration to test the uncovered functional combination logic. The flip-flop includes a reset pin or a set pin coupled to the output of the OR gate. The output of the flip-flop is configured to be observed during a testing of the uncovered functional combination logic to detect defects in the digital circuit.

First claim

What is claimed is:

1. A digital circuit, comprising:
an OR gate having a first input and a second input, the first input coupled to a control signal, the second input coupled to an uncovered functional combination logic of the digital circuit, wherein the first input of the OR gate is configured to be pulled low by the control signal in response to setting the digital circuit in a configuration to test the uncovered functional combination logic; and
a flip-flop having a reset pin or a set pin coupled to an output of the OR gate, wherein an output of the flip-flop is configured to be observed during a testing of the uncovered functional combination logic to detect defects in the digital circuit, wherein the flip-flop is a boundary scan flip-flop or a control flip-flop of the digital circuit.

2. The digital circuit of claim 1 , wherein, in response to the reset pin or the set pin being pulled high during the testing of the uncovered functional combination logic, a last scan shift value of the flip-flop is overridden, and wherein a stuck-at “1” fault condition is observed for the uncovered functional combination logic at the output of the flip-flop.

3. The digital circuit of claim 1 , wherein, in response to the reset pin or the set pin remaining low during the testing of the uncovered functional combination logic, a last scan shift value of the flip-flop is retained, and wherein a stuck-at “0” fault condition is observed for the uncovered functional combination logic at the output of the flip-flop.

4. The digital circuit of claim 1 , further comprising:
a multiplexer having a first input and a second input, the first input coupled to a pad of the digital circuit, and the second input coupled to an LBIST control signal, an output of the multiplexer coupled to the LBIST control signal during LBIST in response to setting the digital circuit in the configuration to test the uncovered functional combination logic, and the output of the multiplexer coupled to a pad of the digital circuit during ATPG functions;
a one-hot decoder circuit configured to generate a first clock signal and second clock signals, the second clock signals provided to the rest of the digital circuit;
a second flip-flop having a clock input, a data input, and an output, the clock input coupled to the output of the one-hot decoder circuit and configured to receive the first clock signal, and the data input coupled to the output of the multiplexer; and
a second OR gate coupled to the output of the second flip-flop, wherein the second OR gate is configured to generate the control signal in response to setting the digital circuit in the configuration to test the uncovered functional combination logic.

5. The digital circuit of claim 1 , further comprising a multiplexer arranged between the output of the OR gate and the reset pin or the set pin of the flip-flop, wherein the multiplexer is configured to couple the OR gate to the flip-flop in response to setting the digital circuit in the configuration to test the uncovered functional combination logic.

6. The digital circuit of claim 1 ,
wherein, in response to the reset pin or the set pin being pulled high during the testing of the uncovered functional combination logic, a last scan shift value of the flip-flop is overridden, and
wherein, in response to the reset pin or the set pin remaining low during the testing of the uncovered functional combination logic, a last scan shift value of the flip-flop is retained.

7. The digital circuit of claim 1 ,
wherein, in response to the reset pin or the set pin being pulled high during the testing of the uncovered functional combination logic, a stuck-at “1” fault condition is observed for the uncovered functional combination logic at the output of the flip-flop, and
wherein, in response to the reset pin or the set pin remaining low during the testing of the uncovered functional combination logic, a stuck-at “0” fault condition is observed for the uncovered functional combination logic at the output of the flip-flop.

8. A digital circuit for testability, the digital circuit comprising:
a multiplexer having a first input, a second input, and an output;
a one-hot decoder circuit configured to generate a first clock signal and second clock signals;
a pipeline flip-flop having a clock input coupled to receive the first clock signal from the one-hot decoder circuit, a data input coupled to the output of the multiplexer, and an output;
a control OR gate having a first input coupled to the output of the pipeline flip-flop and an output configured to generate a control signal;
a functional combination logic circuit;
a test OR gate having a first input coupled to the control signal from the control OR gate and a second input coupled to the functional combination logic circuit; and
a second flip-flop having a reset pin or a set pin coupled to an output of the test OR gate, and an output configured to be observed during testing,
wherein the multiplexer is configured to select between a pad input and a Logic Built-In Self-Test (LBIST) control signal based on a test mode of the digital circuit.

9. The digital circuit of claim 8 , wherein, in response to the reset pin or the set pin being pulled high during testing of the functional combination logic circuit, the second flip-flop is configured to:
override a last scan shift value; and
output a signal indicating a stuck-at “1” fault condition for the functional combination logic circuit.

10. The digital circuit of claim 8 , wherein, in response to the reset pin or the set pin remaining low during testing of the functional combination logic circuit, the second flip-flop is configured to:
retain a last scan shift value; and
output a signal indicating a stuck-at “0” fault condition for the functional combination logic circuit.

11. The digital circuit of claim 8 , wherein the second flip-flop is a boundary scan flip-flop configured to test the functional combination logic circuit near an output pad of the digital circuit.

12. The digital circuit of claim 8 , wherein the second flip-flop is a control flip-flop configured to test the functional combination logic circuit within core logic of the digital circuit.

13. The digital circuit of claim 8 , wherein the second flip-flop is a resettable functional flip-flop of the digital circuit.

14. The digital circuit of claim 8 , further comprising a second multiplexer having a first input coupled to the output of the test OR gate, a second input coupled to a reset signal, and an output coupled to the reset pin or the set pin of the second flip-flop, wherein the second multiplexer is configured to select between the output of the test OR gate and the reset signal based on an operational mode of the digital circuit.

15. A method for testing a digital circuit, the method comprising:
coupling a first input of an OR gate to a control signal;
coupling a second input of the OR gate to an uncovered functional combination logic of the digital circuit;
configuring the first input of the OR gate to be pulled low by the control signal in response to setting the digital circuit in a configuration to test the uncovered functional combination logic;
coupling an output of the OR gate to a reset pin or a set pin of a flip-flop, the flip-flop being a boundary scan flip-flop or a control flip-flop of the digital circuit; and
observing an output of the flip-flop during testing of the uncovered functional combination logic to detect defects in the digital circuit.

16. The method of claim 15 , further comprising:
overriding a last scan shift value of the flip-flop i

Assignees

• St Microelectronics Int Nv

Inventors

• Srinivasan Venkata Narayanan
• Srivastava Umesh Chandra
• Vats Shiv Kumar
• Sharma Manish

Classifications

• G01R31/318541

  Scan latches or cell details · CPC title

• G01R31/318536

  Scan chain arrangements, e.g. connections, test bus, analog signals · CPC title

• G01R31/318597

  JTAG or boundary scan test of memory devices (other scan testing of memories G11C29/32) · CPC title

• G01R31/3187

  Built-in tests · CPC title

• G01R31/31907

  Modular tester, e.g. controlling and coordinating instruments in a bus based architecture · CPC title