Solid-state imaging apparatus and electronic apparatus

Patent metadata

Field	Value
Publication number	US-12364044-B2
Application number	US-202318511444-A
Country	US
Kind code	B2
Filing date	Nov 16, 2023
Priority date	Mar 8, 2017
Publication date	Jul 15, 2025
Grant date	Jul 15, 2025

Abstract

There is provided a imaging device including: an N-type region formed for each pixel and configured to perform photoelectric conversion; an inter-pixel light-shielding wall penetrating a semiconductor substrate in a depth direction and formed between N-type regions configured to perform the photoelectric conversion, the N-type regions each being formed for each of pixels adjacent to each other; a P-type layer formed between the N-type region configured to perform the photoelectric conversion and the inter-pixel light-shielding wall; and a P-type region adjacent to the P-type layer and formed between the N-type region and an interface on a side of a light incident surface of the semiconductor substrate.

First claim

What is claimed is:

1. An imaging device, comprising:
a substrate including a first surface and a second surface opposite to the first surface, wherein the first surface is a light-receiving surface;
a plurality of photoelectric conversion elements in the substrate, wherein each of the plurality of photoelectric conversion elements includes an N-type region;
a first trench disposed between a first photoelectric conversion element and a second photoelectric conversion element of the plurality of photoelectric conversion elements in the substrate in a cross-sectional view, wherein the first trench includes a first material and a second material;
a shallow trench isolation including a third material disposed in the substrate, wherein the third material contacts the first material;
a first P-type region between the first photoelectric conversion element and the first trench in the cross-sectional view; and
a second P-type region adjacent to the first P-type region and between the first photoelectric conversion element and the first surface in the cross-sectional view, wherein an impurity concentration of the second P-type region decreases from a side of the first surface to a side of the second surface in the cross-sectional view.

2. The imaging device according to claim 1 , wherein the first P-type region is formed by doping with impurities from an inner wall of the trench.

3. The imaging device according to claim 1 , wherein the first P-type region is self-aligned with a shape of the first trench.

4. The imaging device according to claim 1 , wherein an impurity material of the first P-type region is boron.

5. The imaging device according to claim 1 , wherein the first material includes polysilicon.

6. The imaging device according to claim 5 , wherein the second material includes silicon oxide.

7. The imaging device according to claim 6 , wherein the third material includes silicon oxide.

8. The imaging device according to claim 5 , wherein the first material includes boron.

9. The imaging device according to claim 8 , wherein the first material is configured to apply a negative bias potential.

10. The imaging device according to claim 1 , further comprising:
a transfer transistor including a transfer gate, wherein the transfer gate includes a vertical transfer gate.

11. The imaging device according to claim 10 , wherein the vertical transfer gate includes a vertical electrode that extended in a depth direction from the second surface in the cross-sectional view.

12. The imaging device according to claim 11 , wherein the vertical electrode includes a first electrode section and a second electrode section in the cross-sectional view.

13. An electronic apparatus comprising:
a signal processor; and
an imaging device, comprising:
a substrate including a first surface and a second surface opposite to the first surface, wherein the first surface is a light-receiving surface;
a plurality of photoelectric conversion elements in the substrate, wherein each of the plurality of photoelectric conversion elements includes an N-type region;
a first trench disposed between a first photoelectric conversion element and a second photoelectric conversion element of the plurality of photoelectric conversion elements in the substrate in a cross-sectional view, wherein the first trench includes a first material and a second material;
a shallow trench isolation including a third material disposed in the substrate, wherein the third material contacts the first material;
a first P-type region between the first photoelectric conversion element and the first trench in the cross-sectional view; and
a second P-type region adjacent to the first P-type region and between the first photoelectric conversion element and the first surface in the cross-sectional view, wherein an impurity concentration of the second P-type region decreases from a side of the first surface to a side of the second surface in the cross-sectional view.

14. The electronic apparatus according to claim 13 , wherein the first P-type region is self-aligned with a shape of the first trench.

15. The electronic apparatus according to claim 13 , wherein an impurity material of the first P-type region is boron.

16. The electronic apparatus according to claim 13 , wherein the first material includes polysilicon.

17. The electronic apparatus according to claim 16 , wherein the second material includes silicon oxide.

18. The electronic apparatus according to claim 17 , wherein the third material includes silicon oxide.

19. The electronic apparatus according to claim 16 , wherein the first material includes boron.

20. The electronic apparatus according to claim 19 , wherein the first material is configured to apply a negative bias potential.

Assignees

• Sony Semiconductor Solutions Corp

Inventors

• Uchida Tetsuya
• Suzuki Ryoji
• ANSAI Hisahiro
• Ueda Yoichi
• Yoshida Shinichi
• Takeya Yukari
• Hirano Tomoyuki
• Mori Hiroyuki
• Nomura Hirotoshi
• Kudoh Yoshiharu
• OHURA Masashi
• Iwabuchi Shin

Classifications

• H10F39/80373 Primary

  characterised by the gate of the transistor · CPC title

• H10F39/8063

  Microlenses · CPC title

• H10F39/807

  Pixel isolation structures · CPC title

• H10F39/199

  Back-illuminated image sensors · CPC title

• H10F39/18

  Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors · CPC title