Method for preparing array substrate and array substrate

Patent metadata

Field	Value
Publication number	US-12364009-B2
Application number	US-202117800337-A
Country	US
Kind code	B2
Filing date	Dec 29, 2021
Priority date	Mar 1, 2021
Publication date	Jul 15, 2025
Grant date	Jul 15, 2025

Abstract

A method for preparing an array substrate and an array substrate. The method for preparing an array substrate includes: depositing a first metal layer, an insulating layer, an active layer and a doping layer on the substrate; forming a photoresist on doping layer by using a first photomask process, and etching the photoresist to form a gate and a channel; depositing a second metal layer on the substrate; using the second photomask process to form the source-drain metal layer; depositing a passivation layer on the substrate; using the third photomask process to form a pixel electrode layer.

First claim

What is claimed is:

1. A method for preparing an array substrate, comprising the following steps:
first deposition, comprising: depositing a first metal layer, an insulating layer, an active layer and a doping layer on a substrate in sequence;
first photomask, comprising: forming a photoresist on the doped layer by a first photomask process, and forming a gate and a channel by etching the first metal layer, the insulating layer, the active layer, and the doped layer;
second deposition, comprising: depositing a second metal layer on the substrate;
second photomask, comprising: forming a source-drain metal layer by using a second mask process to pattern the second metal layer;
third deposition, comprising: depositing a passivation layer on the substrate; and
third photomask, comprising: forming a pixel electrode pattern by using a third photomask process to pattern the passivation layer, and forming a pixel electrode layer on the passivation layer according to the pixel electrode pattern.

2. The method for preparing the array substrate according to claim 1 , wherein the first photomask, comprises the followings steps:
etching the doping layer, the active layer, the insulating layer and the first metal layer, respectively;
exposing and developing the photoresist, and removing the photoresist to form the gate and the channel.

3. The method for preparing the array substrate according to claim 2 , wherein in the step of etching the doping layer, the active layer, the insulating layer and the first metal layer, respectively: an etching method of the doping layer, the active layer and the insulating layer is dry etching; and an etching method of the first metal layer is wet etching.

4. The method for preparing the array substrate according to claim 2 , wherein the step of after exposing and developing the photoresist, removing the photoresist to form the gate and the channel, comprises the following steps:
removing the photoresist for a first time to retain the photoresist on the doping layer facing a thin film transistor area;
etching the doping layer facing the thin film transistor area to form the channel; and
removing the photoresist remaining on the doping layer for a second time to form the gate.

5. The method for preparing an array substrate according to claim 4 , wherein in the step of removing the photoresist for the first time to retain the photoresist on the doping layer facing a thin film transistor area, and removing the photoresist for the first time is completed in the same process.

6. The method for preparing an array substrate according to claim 4 , wherein in the step of removing the photoresist remaining on the doping layer for the second time to form the gate, the two photoresists located on both sides of the channel are irradiated with light by means of a mask and removed by the developer.

7. The method for preparing an array substrate according to claim 6 , wherein the removing the two photoresists located on both sides of the channel is completed in the same process.

8. The method for preparing the array substrate according to claim 4 , wherein in the step of etching the doping layer facing the thin film transistor area to form the channel, an etching method of the doping layer is dry etching.

9. The method for preparing the array substrate according to claim 1 , wherein
a thin film transistor area, a storage capacitor area, a pixel area, a through hole area and a binding area are arranged on the substrate at intervals; the first metal layer, the insulating layer, the active layer, the doping layer and the second metal layer are arranged on the thin film transistor area in sequence;
the first metal layer, the insulating layer, the active layer and the second metal layer are arranged on the storage capacitor area in sequence;
the first metal layer, the insulating layer, the active layer and the second metal layer are arranged on the through hole area in sequence;
the first metal layer, the insulating layer and the active layer are arranged on the binding area in sequence; and
the passivation layer covers the substrate.

10. The method for preparing the array substrate according to claim 9 , wherein
a first spacing area is formed at intervals between the photoresist facing the thin film transistor area and the photoresist facing the storage capacitor area;
a second spacing area is formed at intervals between the photoresist facing the storage capacitor area and the photoresist facing the through hole area, the second spacing area facing the pixel area; and
a third spacing area is formed at intervals between the photoresist facing the through hole area and the photoresist facing the binding area, and the etching of the first spacing area, the second spacing area and the third spacing area are completed in the same dry etching process.

11. The method for preparing the array substrate according to claim 10 , wherein the first metal layer in the first spacing area, the first metal layer in the second spacing area and the first metal layer in the third spacing area are completed in the same wet etching process.

12. The method for preparing the array substrate according to claim 9 , wherein the second metal layer facing the thin film transistor area, the second metal layer facing the storage capacitor area, and the two second metal layer facing the through hole area are formed in the same process.

13. The method for preparing the array substrate according to claim 1 , wherein, in the step of third photomask: the passivation layer and the pixel electrode layer are respectively formed by a photoresist lift-off technique.

14. The method for preparing the array substrate according to claim 1 , wherein the active layer is an amorphous silicon layer.

15. The method for preparing the array substrate according to claim 1 , wherein the pixel electrode layer is an indium tin oxide layer.

16. The method for preparing the array substrate according to claim 1 , wherein the insulating layer is silicon oxide or silicon nitride.

Assignees

• Chongqing Advance Display Tech Research
• Chongqing Hkc Optoelectronics Tech Co Ltd

Inventors

• Zhang Hejing
• Liu Zhen

Classifications

• H10D84/01

  Manufacture or treatment · CPC title

• H10D86/441 Primary

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D86/0231 Primary

  using masks, e.g. half-tone masks · CPC title

• Y02P70/50

  Manufacturing or production processes characterised by the final manufactured product · CPC title