Semiconductor device

Patent metadata

Field	Value
Publication number	US-12362666-B2
Application number	US-202318153446-A
Country	US
Kind code	B2
Filing date	Jan 12, 2023
Priority date	Jan 13, 2022
Publication date	Jul 15, 2025
Grant date	Jul 15, 2025

Abstract

A semiconductor device may include: a flying capacitor connected between a first node and a second node; a first inductor having a first end connected to the flying capacitor through the first node and a second end connected to an output node; and a second inductor having a first end connected to the flying capacitor through the second node and a second end connected to the output node, wherein the semiconductor device is configurable in a plurality of different states based on a plurality of different operational phases, and wherein the flying capacitor is configured to float in a first phase, is configured to be discharged through the first inductor in a second phase that is different from the first phase, and is configured to be charged through the second inductor in a third phase that is different from the first phase and the second phase.

First claim

What is claimed is:

1. A semiconductor device comprising:
a flying capacitor connected between a first node and a second node;
a first inductor having a first end connected to the flying capacitor through the first node and a second end connected to an output node; and
a second inductor having a first end connected to the flying capacitor through the second node and a second end connected to the output node,
wherein the semiconductor device is configurable in a plurality of different states based on a plurality of different operational phases, and
wherein the flying capacitor is configured to float in a first phase, is configured to be discharged through the first inductor in a second phase that is different from the first phase, and is configured to be charged through the second inductor in a third phase that is different from the first phase and the second phase.

2. The semiconductor device of claim 1 , wherein in the first phase:
the first inductor is electrically connected to an input node through the first node,
the second inductor is electrically connected to the input node through the second node, and
the first inductor and the second inductor are energized by a difference between an input voltage at the input node and an output voltage at the output node.

3. The semiconductor device of claim 2 , further comprising:
a first connection switch between the input node and the first node; and
a second connection switch between the input node and the second node,
wherein the first connection switch and the second connection switch are in an on state in the first phase.

4. The semiconductor device of claim 3 , wherein in the second phase:
the first inductor is electrically connected to the flying capacitor through the first node, and
the first inductor is de-energized by a difference between a voltage at the flying capacitor and the output voltage.

5. The semiconductor device of claim 4 , wherein a first applying voltage for the first inductor applied to the first node is 0.5 times the input voltage.

6. The semiconductor device of claim 4 , further comprising
a third connection switch between a third node connected to the flying capacitor and the ground node,
wherein the third connection switch is in the on state in the second phase.

7. The semiconductor device of claim 3 , wherein in the third phase:
the second inductor is electrically connected to the flying capacitor through the second node, and
the second inductor is de-energized by a difference between the input voltage and a sum of the voltage at the flying capacitor and the output voltage.

8. The semiconductor device of claim 7 , wherein a second applying voltage for the second inductor applied to the second node is 0.5 times the input voltage.

9. The semiconductor device of claim 7 , further comprising
a fourth connection switch between a third node connected to the flying capacitor and the second node,
wherein the fourth connection switch is in the on state in the third phase.

10. The semiconductor device of claim 1 , wherein
when a first inductor current of the first inductor becomes greater than a second inductor current of the second inductor,
a voltage at the flying capacitor is reduced so that the first inductor current becomes identical to the second inductor current, and
when the first inductor current of the first inductor becomes less than the second inductor current of the second inductor,
the voltage at the flying capacitor is increased so that the first inductor current becomes identical to the second inductor current.

11. A semiconductor device comprising:
a first connection switch configured to selectively supply an input voltage to a first inductor and a first end of a flying capacitor;
a second connection switch configured to selectively supply a ground voltage to a second end of the flying capacitor;
a third connection switch configured to selectively supply the input voltage to a first end of a second inductor; and
a fourth connection switch configured to supply a voltage at the second end of the flying capacitor to the first end of the second inductor.

12. The semiconductor device of claim 11 , wherein in the first phase,
the first connection switch and the third connection switch are in an on state,
the second connection switch and the fourth connection switch are in an off state, and
the first inductor and the second inductor are energized by a difference between the input voltage and an output voltage at an output node, the first inductor being connected between the output node and the flying capacitor.

13. The semiconductor device of claim 11 , wherein in the second phase,
the second connection switch and the third connection switch are in an on state,
the first connection switch and the fourth connection switch are in an off state,
the first inductor is de-energized by a difference between a voltage at the flying capacitor and an output voltage at an output node, the first inductor being connected between the output node and the flying capacitor, and
the second inductor is energized by a difference between the input voltage and the output voltage.

14. The semiconductor device of claim 13 , wherein a first applying voltage for the first inductor is 0.5 times the input voltage.

15. The semiconductor device of claim 11 , wherein in the second phase,
the first connection switch and the fourth connection switch are in an on state,
the second connection switch and the third connection switch are in an off state,
the first inductor is energized by a difference between the input voltage and an output voltage at an output node, the first inductor being connected between the output node and the flying capacitor, and
the second inductor is de-energized by a difference between the input voltage and a sum of a voltage at the flying capacitor and the output voltage.

16. The semiconductor device of claim 15 , wherein a second applying voltage for the second inductor applied to the second node is 0.5 times the input voltage.

17. The semiconductor device of claim 11 , wherein
when a first inductor current of the first inductor becomes greater than a second inductor current of the second inductor,
a voltage at the flying capacitor is reduced so that the first inductor current becomes identical to the second inductor current, and
when the first inductor current of the first inductor becomes less than the second inductor current of the second inductor,
the voltage at the flying capacitor is increased so that the first inductor current becomes identical to the second inductor current.

18. A semiconductor device comprising:
a first flying capacitor connected between a first node and a third node;
a second flying capacitor connected between a fifth node and a seventh node;
a first inductor having a first end connected to the first flying capacitor through the first node and a second end connected to an output node;
a second inductor having a first end connected to the first flying capacitor through a first connection switch between a second node and the third node and a second end connected to the output node;
a third inductor having a first end connected to the second flying capacitor through the fifth node and a second end connected to the output node;
a fourth inductor having a first end connected to the second flying capacitor through a second connection switch between a sixth node and the seventh node and a second end connected to the output node;
a third connection switch connected between the second node and the

Assignees

• Samsung Electronics Co Ltd
• Korea Advanced Inst Sci & Tech

Inventors

• Yang Junhyeok
• Cho Jeong-Hyun
• Park Jeongpyo
• Kong Tae-Hwang
• Kim Hyun-Sik
• Bae Hong-Hyun

Classifications

• H02M3/158 Primary

  including plural semiconductor devices as final control devices for a single load · CPC title

• H02M3/1584

  with a plurality of power processing stages connected in parallel · CPC title

• H02M3/1586

  switched with a phase shift, i.e. interleaved · CPC title

• H02M1/0095

  Hybrid converter topologies, e.g. NPC mixed with flying capacitor, thyristor converter mixed with MMC or charge pump mixed with buck · CPC title

• H02M3/07 Primary

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title