Method and wafer processing furnace for forming an epitaxial stack on a plurality of substrates

US12362174B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12362174-B2
Application numberUS-202318153272-A
CountryUS
Kind codeB2
Filing dateJan 11, 2023
Priority dateJan 13, 2022
Publication dateJul 15, 2025
Grant dateJul 15, 2025

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Abstract

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A method and a wafer processing furnace for forming an epitaxial stack on a plurality of substrates is provided. In a preferred embodiment, the method comprises providing the plurality of substrates to a process chamber. A plurality of deposition cycles is executed, thereby forming the epitaxial stack on the plurality of substrates. The epitaxial stack comprises a plurality of epitaxial pairs, wherein the epitaxial pairs each comprises a first epitaxial layer and a second epitaxial layer, the second epitaxial layer being different from the first epitaxial layer. Each deposition cycle comprises a first deposition pulse and a second deposition pulse. The first deposition pulse comprises a provision of a first reaction gas mixture to the process chamber, thereby forming the first epitaxial layer. The second deposition pulse comprises a provision of a second reaction gas mixture to the process chamber, thereby forming the second epitaxial layer. The first deposition pulse or the second deposition pulse further comprises a provision of a dopant precursor gas to the process chamber.

First claim

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The invention claimed is: 1. A method of forming an epitaxial stack on a plurality of substrates, the method comprising: providing the plurality of substrates to a process chamber; and executing a plurality of deposition cycles, thereby forming the epitaxial stack on the plurality of substrates, the epitaxial stack comprising a plurality of epitaxial pairs, wherein the epitaxial pairs each comprise a first epitaxial layer and a second epitaxial layer, the second epitaxial layer being different from the first epitaxial layer, wherein each deposition cycle, of the plurality of deposition cycles, comprises: a first deposition pulse comprising a provision of a first reaction gas mixture to the process chamber, thereby forming the first epitaxial layer, and a second deposition pulse comprising a provision of a second reaction gas mixture to the process chamber, the second reaction gas mixture being different from the first reaction gas mixture, thereby forming the second epitaxial layer; wherein the first deposition pulse or the second deposition pulse further comprises a provision of a dopant precursor gas to the process chamber; and wherein a dopant concentration in at least one of the first epitaxial layer and the second epitaxial layer: gradually increases from an upper surface of the at least one of the first epitaxial layer and the second epitaxial layer to a center of the at least one of the first epitaxial layer and the second epitaxial layer; and gradually decreases from the center of the at least one of the first epitaxial layer and the second epitaxial layer to a lower surface of the at least one of the first epitaxial layer and the second epitaxial layer. 2. The method according to claim 1 , wherein the provision of the dopant precursor gas to the process chamber reduces stress in the epitaxial stack. 3. The method according to claim 1 , wherein the provision of the dopant precursor gas is performed simultaneously with the provision of the first reaction gas mixture or simultaneously with the provision of the second reaction gas mixture. 4. The method according to claim 1 , wherein the first epitaxial layer comprises a first semiconductor material and wherein the provision of the first reaction gas mixture comprises providing first semiconductor material precursors, the second epitaxial layer comprises a second semiconductor material being different than the first semiconductor material and wherein the provision of the second reaction gas mixture comprises providing a second semiconductor material precursor, and the dopant precursor gas is provided simultaneously with the provision of the first reaction gas mixture. 5. The method according to claim 1 , wherein the dopant precursor gas is at least one of a Group IIIA, a Group IVA or a Group VA element-containing compound. 6. The method according to claim 4 , wherein: the first semiconductor material precursors comprise a germanium-containing compound and a first silicon-containing compound, and the second semiconductor material precursor comprises substantially a second silicon-containing compound. 7. The method according to claim 6 , wherein the germanium-containing compound comprised in the first semiconductor material precursors is at least one of mono-germane or a halo-germane. 8. The method according to claim 6 , wherein the first silicon-containing compound comprised in the first semiconductor material precursors or the second silicon-containing compound comprised substantially in the second semiconductor material precursor is a mono-silane, a high order silane or a cyclic silane. 9. The method according to claim 8 , wherein the high order silane is a high order straight chain silane or high order branched silane. 10. The method according to claim 9 , wherein the high order straight chain silane is trisilane. 11. The method according to claim 9 , wherein the high order branched silane is neopentasilane. 12. The method according to claim 8 , wherein the cyclic silane is cyclohexasilane. 13. The method according to claim 1 , wherein the process chamber is maintained at a temperature in a range of 300° C. to 600° C. 14. A method of forming an epitaxial stack on a plurality of substrates; the method comprising: providing the plurality of substrates to a process chamber; and forming the epitaxial stack on the plurality of substrates, comprising a formation of a first epitaxial layer alternatingly and repeatedly with a formation of a second epitaxial layer, thereby forming a plurality of epitaxial pairs, wherein: each of the first epitaxial layers comprises a germanium concentration in a range of about 15 atomic % to about 30 atomic % and a silicon concentration in a range of about 70 atomic % to about 85 atomic %; each of the second epitaxial layers comprises a silicon concentration of about 100 atomic %; and a dopant concentration of a dopant in the first epitaxial layer: gradually increases from an upper surface of the first epitaxial layer to a center of the first epitaxial layer; and gradually decreases from the center of the first epitaxial layer to a lower surface of the first epitaxial layer. 15. The method according to claim 14 , wherein a concentration of the dopant in the first epitaxial layer is less than 10 atomic %. 16. The method according to claim 14 , wherein the dopant is provided in the process chamber simultaneously during the formation of the first epitaxial layer. 17. The method according to claim 14 , wherein a number of epitaxial pairs is at least 50. 18. The method according to claim 14 , wherein the formation of the first epitaxial layer comprises providing a first semiconductor material precursors, the first semiconductor material precursors comprising a germanium-containing compound and a first silicon-containing compound; and wherein the formation of the second epitaxial layer comprises providing a second semiconductor material precursor, the second semiconductor material precursor comprising substantially a second silicon-containing compound. 19. The method according to claim 18 , wherein the first silicon-containing compound comprised in the first semiconductor material precursors or the second silicon-containing compound comprised substantially in the second semiconductor material precursor is a mono-silane, a high order silane or a cyclic silane.

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What does patent US12362174B2 cover?
A method and a wafer processing furnace for forming an epitaxial stack on a plurality of substrates is provided. In a preferred embodiment, the method comprises providing the plurality of substrates to a process chamber. A plurality of deposition cycles is executed, thereby forming the epitaxial stack on the plurality of substrates. The epitaxial stack comprises a plurality of epitaxial pairs, …
Who is the assignee on this patent?
Asm Ip Holding Bv
What technology area does this patent fall under?
Primary CPC classification H10P14/24. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 15 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).