Display substrate, display panel, display apparatus, and method of fabricating display substrate

Patent metadata

Field	Value
Publication number	US-12361889-B2
Application number	US-202217589810-A
Country	US
Kind code	B2
Filing date	Jan 31, 2022
Priority date	Oct 15, 2018
Publication date	Jul 15, 2025
Grant date	Jul 15, 2025

Abstract

A display substrate having a display area and a gate-on-array (GOA) area outside the display area is provided. The display substrate includes a base substrate; a plurality of GOA signal lines on the base substrate and in the GOA area; and a first signal line in the GOA area, at least a portion of the first signal line being on a side of the plurality of GOA signal lines away from the base substrate. An orthographic projection of the first signal line on the base substrate at least partially covers an orthographic projection of at least one of a first clock signal line, a second clock signal line, a start signal line, a high voltage power line, or a low voltage power line on the base substrate.

First claim

What is claimed is:

1. A display substrate having a display area and a gate-on-array (GOA) area outside the display area, comprising:
a base substrate;
a plurality of GOA signal lines on the base substrate and in the GOA area;
a first signal line in the GOA area, at least a portion of the first signal line being on a side of the plurality of GOA signal lines away from the base substrate;
a light shielding layer on the base substrate;
an insulating layer on a side of the light shielding layer away from the base substrate;
a plurality of thin film transistors in the display area;
a planarization layer on a side of the GOA signal line away from the base substrate; and
a first signal line in the GOA area and on a side of the planarization layer away from the base substrate, and is connected electrically in parallel with a second part of the light shielding layer in the GOA area, the second part spaced apart from the first part;
wherein the plurality of GOA signal lines comprise a first clock signal line, a second clock signal line, a start signal line, a high voltage power line, and a low voltage power line;
an orthographic projection of the first signal line on the base substrate at least partially covers an orthographic projection of at least one of the first clock signal line, the second clock signal line, the start signal line, the high voltage power line, or the low voltage power line on the base substrate;
the GOA signal line is on a side of the insulating layer away from the light shielding layer, and is connected electrically in parallel with a first part of the light shielding layer, the first part being in the GOA area;
the display substrate comprises a plurality of first vias extending through the insulating layer in the GOA area;
the GOA signal line is electrically connected to the first part of the light shielding layer through the plurality of first vias respectively, thereby connecting the GOA signal line and the first part of the light shielding layer electrically in parallel;
the light shielding layer further comprises a plurality of light shielding blocks on the base substrate and in the display area, a respective one of the plurality of light shielding blocks on a side of an active layer of the plurality of thin film transistors closer to the base substrate for shielding light from irradiating on the active layer;
the first part of the light shielding layer and the plurality of light shielding blocks are in a same layer and comprise a same material;
the display substrate comprises a plurality of second vias extending through the insulating layer and the planarization layer in the GOA area; and
the first signal line is electrically connected to the second part of the light shielding layer through the plurality of second vias respectively, thereby connecting the first signal line and the second part of the light shielding layer electrically in parallel.

2. The display substrate of claim 1 , wherein the orthographic projection of the first signal line on the base substrate at least partially covers a combination of orthographic projections of the first clock signal line, the second clock signal line, the start signal line, the high voltage power line, and the low voltage power line on the base substrate.

3. The display substrate of claim 1 , further comprising a plurality of drive circuits in the GOA area;
wherein the plurality of drive circuits comprise at least one of a gate drive circuit configured to transmit gate scanning signals to gate electrodes of data write transistors in a pixel driving circuits in a display area, a light emission control drive circuit configured to transmit light emission control signals to gate electrodes of light emission control transistors in the pixel driving circuits in the display area, and a reset control drive circuit configured to transmit reset control signals to reset transistors in the pixel driving circuits in the display area; and
the orthographic projection of the first signal line on the base substrate at least partially covers an orthographic projection of the light emission control drive circuit on the base substrate.

4. The display substrate of claim 3 , wherein the orthographic projection of the first signal line on the base substrate further at least partially covers an orthographic projection of the gate drive circuit on the base substrate.

5. The display substrate of claim 3 , wherein the orthographic projection of the first signal line on the base substrate covers an orthographic projection of at least one light emission control shift register of the light emission control drive circuit on the base substrate.

6. The display substrate of claim 3 , wherein the orthographic projection of the first signal line on the base substrate covers an orthographic projection of at least one light emission control shift register unit of the light emission control drive circuit on the base substrate, and covers an orthographic projection of at least one shift register unit of the gate drive circuit.

7. The display substrate of claim 6 , wherein an orthographic projection of the respective one of the plurality of light shielding blocks on the base substrate covers an orthographic projection of the active layer of the plurality of thin film transistors on the base substrate.

8. The display substrate of claim 1 , further comprising a plurality of pixel driving circuits, a respective pixel driving circuit of the plurality of pixel driving circuit comprising a thin film transistor, a planarization layer, and a relay electrode;
wherein the planarization layer is on a side of the thin film transistor away from the base substrate, covering the thin film transistor;
the relay electrode is on a side of the planarization layer away from the base substrate;
the thin film transistor comprises an active layer on the base substrate, a gate electrode on a side of the active layer away from the base substrate, a first electrode and a second electrode on a side of the gate electrode away from the base substrate, the relay electrode being electrically connected to one of the first electrode and the second electrode through a via extending through the planarization layer; and
the first signal line is in a same layer as the relay electrode.

9. The display substrate of claim 1 , comprising at least one opening in the second part of the light shielding layer.

10. The display substrate of claim 1 , wherein the first part and the second part of the light shielding layer, and the plurality of light shielding blocks are in a same layer and comprise a same material.

11. The display substrate of claim 1 , further comprising a second signal line in the display area and on a side of the planarization layer away from the base substrate, and is connected electrically in parallel with a third part of the light shielding layer in the display area, the third part spaced apart from the first part and spaced apart from the second part; and
a plurality of third vias extending through the insulating layer and the planarization layer in the display area;
wherein the second signal line is electrically connected to the third part of the light shielding layer through the plurality of third vias respectively, thereby connecting the second signal line and the third part of the light shielding layer electrically in parallel.

12. The display substrate of claim 11 , wherein the first part, the second part, and the third part of the light shielding layer, and the plurality of light shielding blocks are in a same layer and comprise a same material.

13. The display substrate of claim 11 , wherein the second signal line is a ground volta

Assignees

• Boe Technology Group Co Ltd

Inventors

• Tian Hongwei
• Niu Yanan
• Wang Chunyang
• Li Dong
• Liu Zheng
• Zhang Shuai

Classifications

• H10K50/865

  comprising light absorbing layers, e.g. light-blocking layers · CPC title

• H10K59/8792

  comprising light absorbing layers, e.g. black layers · CPC title

• H10K59/1213

  the pixel elements being TFTs · CPC title

• H10K59/131

  Interconnections, e.g. wiring lines or terminals · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title